Memory reference instruction

Memory reference instruction

• 1.
  MEMORY REFERNCE INSTRUCTIONSPRESENTED BY: SURBHI
• 2.
  MEMORY REFERENCE INSTRUCTIONSThe bits in IR 12 to 14 determines the memory reference instruction type if the bits were from 000 to 110. Used here a 3 by 8 decoder is used to decode the 3 bits to 8 lines D0 to D7, although D7 not used here. The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or during timing signal T3when I = 1. Data from memory must be accessed to processor during T4.
• 3.
  AND TO ACD 0 T 4 : DR  M[AR] D 0 T 5 : AC  AC DR, SC  0 ADD TO AC D 1 T 4 : DR  M[AR] D 1 T 5 : AC  AC+ DR, E  COUT, SC  0
• 4.
  LDA : LOADTO AC D 2 T 4 : DR  M[AR] D 2 T 5 : AC  DR, SC  0 STA : STORE AC D 3 T 4 : M[AR]  AC, SC  0
• 5.
  BUN : BRANCHUNCONDITIONALLY D 4 T 4 : PC  AR, SC  0 BSA: BRANCH AND SAVE RETURN ADDRESS D 5 T 4 : M[AR]  PC, AR  AR+ 1 D 5 T 5 : PC  AR, SC  0
• 6.
  20 PC=21 AR=135136 20 21 135 PC=136 (b) memory and pc after execution (a) Memory ,PC AND AR AT TIME T4 MEMORY MEMORY Example of BSA 0 BSA 135 Next instruction Subroutine 1 BUN 135 0 BSA 135 Next instruction Subroutine 1 BUN 135
• 7.
  ISZ : INCREMENTAND SKIP IF ZERO D 6 T 4 : DR  M[AR] D 6 T 5 : DR  DR+1 D 6 T 6 : M[AR]  DR, if(DR=0) then (PC  PC + 1, SC  0