Ch-7

Low Power Arithmetic Components

Preethi S Awate
Content

• Adder
• Adder Types
 Full Adder
 Ripple Carry Adder
 Carry Lookahead Adder
 Carry Select Adder (CSA)
 Constant Block Width CSA
 Variable Block Width Carry Skip Adder
 Conditional Sum Adder (CSMA)
• Multiplier
• Multiplier Types
 Bit Array Multiplier
 One Cell of an Array Multiplier
 Wallace Tree Multiplier
 Dadda multiplier
Adder
An adder in digital circuits is used to perform binary addition. The adders designed using static CMOS
logic are evaluated based on their dynamic power dissipation, which is mainly influenced by the
number of logic transitions during operation. Fewer transitions typically mean lower power
consumption.
Different adder designs (like ripple carry, carry lookahead, etc.) have been analysed using gate-level
simulation, detailed circuit simulation, and physical measurement to estimate their power efficiency and
performance.
Adder Types:

Full Adder
A full adder is a digital circuit that adds three binary inputs: two significant bits (Aᵢ and Bᵢ) and a carry-in (Cᵢ).
It produces two outputs: a sum bit (Sᵢ) and a carry-out (Cᵢ ₊₁). The circuit shown implements this using two half
adders and additional logic.

• A Full Adder adds three 1-bit inputs: A, B, and Carry-in

(Cin), and produces:
Sum (S) and Carry-out (Cout).
• Equations:
Sum = A ⊕ B ⊕ Cin
Cout = (A · B) + (B · Cin) + (A · Cin)
• These are implemented using XOR, AND, and OR gates.
• This is the basic unit in all multi-bit adders.
Ripple Carry Adder
A ripple carry adder is made by connecting multiple full adders in series.
In this 16-bit ripple carry adder, each full adder computes one bit of the sum and passes its carry to the next stage.
The carry ripples from the least significant bit to the most significant bit.

• Each A 16-bit ripple carry adder uses 16 full adder (FA)

blocks.
• FA adds Aᵢ, Bᵢ, and carry-in Cᵢ to produce sum Sᵢ and carry-
out Cᵢ₊₁.
• Sum: Sᵢ = Aᵢ ⊕ Bᵢ ⊕ Cᵢ
• Carry-out: Cᵢ₊₁ = (Aᵢ · Bᵢ) + (Cᵢ · (Aᵢ ⊕ Bᵢ))
• Carry-out of each FA becomes carry-in for the next stage.
• Correct addition occurs, but delay increases linearly with
each stage.
Carry Lookahead Adder
A type of adder that computes carry outputs for each bit position in
parallel using propagate and generate signals, reducing delay compared to
ripple carry.
A CLA that adds 16-bit numbers by dividing them into smaller blocks
(e.g., 4-bit), with hierarchical lookahead logic for fast carry generation
across all 16 bits.

• 16-bit adder split into four 4-bit blocks, each with 4 full
adders.
• Each adder generates sum, propagate (P = A⊕B), and
generate (G = A·B).
• Block-level lookahead logic computes carries in parallel:
e.g., C₁ = G₀ + P₀·Cin,
C₂ = G₁ + P₁·G₀ + P₁·P₀·Cin
• Second-level lookahead computes inter-block carries.
• Final output is the carry-out (C₁₆) from AND-OR of
global P and G.
• Uses 4-bit modules (14 gates each), reducing delay to
~log₂N.
• Faster than ripple carry due to parallel carry computation.
Fig 7.10 16-Bit Carry Lookahead Adder
Carry Select Adder (CSA)
A Carry Select Adder improves speed by dividing the adder into blocks, where each block computes two possible sums
in parallel — one assuming carry-in = 0 and the other assuming carry-in = 1. A multiplexer then selects the correct sum
based on the actual carry input. This reduces delay compared to ripple carry adders.

• The 16-bit adder is divided into four 4-bit blocks: bits 3:0, 7:4,
11:8, and 15:12.
• Each block has two Ripple Carry Adders (RCA):
•One assumes carry-in = 0
•One assumes carry-in = 1
• Both RCAs compute their respective sums in parallel.
• A 2:1 multiplexer (MUX) selects the correct output based on the
actual carry-in, which is computed using Carry Lookahead
Logic.
• The carry lookahead logic generates carries between blocks: c₁,
c₂, c₃.
• The final result S₀ to S₁₅ is formed by selecting the correct sum
from each block's MUX.
Constant Block Width CSA
An adder that divides bits into equal-sized blocks. Each block uses skip logic to quickly pass carry if all propagate
signals are high, reducing delay. A 16-bit adder built using blocks of 3 bits (optimal). Carry skip logic is applied to
each block, improving speed over ripple carry. Designed by dropping 2 MSBs from an 18-bit structure.

• The 16-bit adder is divided into equal-sized blocks of 3 full adders (FA) in each.
• Each block uses a Carry Skip Logic that allows the carry to skip over the entire block if all propagate signals
in the block are high.
• If propagate signal (P), P₀·P₁·P₂ = 1, then the input carry skips the block and directly moves to the next.
• This avoids ripple delay within the block when carry doesn’t need to wait.
• The final design is based on an 18-bit structure; the 2 MSBs are dropped to make it 16-bit.
• Uses single-level skip logic (simpler, faster)
Variable Block Width Carry Skip Adder
It divides the adder into blocks of different sizes, each with skip logic to speed up carry propagation. It allows
carry to bypass blocks when all propagate signals are high. By adjusting block sizes, it reduces delay and
improves performance compared to fixed-block skip adders.

• The adder is 16-bit, split into blocks of variable widths (e.g., 2-4-4-3-2-1).
• Each block contains Full Adders (FA) and a Skip logic unit.
• The skip unit checks if all bits in the block propagate the carry (Pi = Ai ⊕ Bi = 1).
• If all propagate bits are 1, carry can "skip" the entire block, improving speed.
• The adder supports multiple levels of skip paths, enabling faster carry propagation across wider regions.
• Turrini Algorithm is used to optimize block groupings and skip logic for low dynamic power and better
performance.
 Conditional Sum Adder (CSMA)
A fast adder that precomputes sum and carry for both carry-in values (0 and 1), then uses multiplexers to select the correct
result based on the actual carry, enabling faster addition by avoiding long carry propagation delays

• Divides 8 bits into blocks of 2 bits each.

• Uses Sklansky “H” cells (a type of parallel prefix adder
designed for high-speed binary addition.) to compute
sum and carry for both Cin = 0 and Cin = 1.
• 2:1 multiplexers select the correct output based on the
actual carry-in.
• Carry is computed quickly using logic blocks
(FC = AND + OR).
• Blocks are recursively combined, reducing delay.
• Faster than ripple carry as it avoids carry propagation
delay.
• In choosing an adder for a particular application, several things must be considered, including
speed, size, and dynamic power consumption.
• The speed is usually considered to be the worst case number of gate delays from input to the
slowest output (typically the most significant sum bit).
• Table 7.5 presents the worst case number of gate delays for the six adders for the purposes of this
chapter, all gates are assumed to have the same delay, regardless of the fan-in or fan-out.
• The size of each adder is approximated to a first order by the number of gates, which is given in
Table 7.6.
• The actual area required for a given adder will depend on the types of gates (i.e., three or four
input gates require more area than two input gates), the amount of wiring area, and the available
form factor, as will be seen in the next subsection.
Multiplier

A multiplier is a digital circuit used to perform binary multiplication of two numbers. It takes two binary inputs and
generates a product, often using repeated addition, shifting, or optimized algorithms like Booth or array multiplication.
• Multiplier design affects both power and delay.
• Focus has shifted from adders to multipliers in recent research.
• Chau and Powell studied matrix-matrix multipliers, optimizing algorithm partitioning.
• Lemonds and Shetti showed that latches help reduce power by preventing glitches.
• Efficient design choices can significantly reduce power dissipation in array multipliers.

Multiplier Types:
• Multiplication can be seen as repeated shifts and additions. It can be implemented using just an adder, shift
register, and control logic — making it compact but slow. It's a serial process, requiring (n−1) additions for n-bit
operands, leading to higher delay.
Bit Array Multiplier
A Bit Array Multiplier is used to multiply two binary numbers using an array of logic gates. It generates partial products
using AND gates, and then adds them in a grid-like structure using half adders and full adders. The outputs are
summed diagonally, and the result is a binary product.

• The array multiplies two 8-bit binary numbers to produce a 16-bit

result (P0–P15).Each cell in the 8×8 grid operates on one bit from
the multiplicand (X0–X7) and multiplier (Y0–Y7).
• Partial products are generated using AND gates and summed
diagonally using full adders (FA) and half adders (RA).
• The first row has only AND gates, middle rows use full adders to
add products and carries, and the last row acts as a ripple carry
adder to generate the final output.
• The final 16-bit result is collected from the bottom and right edges,
with P0 as the least significant bit and P15 as the most significant.
 One Cell of an Array Multiplier
Each cell takes a bit from the multiplicand and multiplier, generates a partial product using an AND gate, and
adds it with previous sums using a half or full adder. It passes sum and carry to the next cells for final output.

Figure 7.26 One Cell of an Array Multiplier

• The vertical and horizontal lines represent input bits: Aᵢ (from the multiplicand) and B ⱼ (from the multiplier),
respectively.
• These bits enter an AND gate, which generates a partial product.
• This partial product is then fed into a Full Adder, which also takes input from the previous cell’s sum and carry.
• The Full Adder processes these three inputs and produces a new sum and carry.
• The sum output moves diagonally to the next stage, while the carry is passed downward to the next row of adders.
Wallace Tree Multiplier
A Wallace Tree Multiplier is a fast digital circuit used to multiply binary numbers. It reduces partial products in parallel
using layers of half and full adders, arranged in a tree-like structure, to speed up the summation process and reduce overall
multiplication time.

• The figure shows how partial products (Ab₀ to Ab₇) are reduced
using a tree structure of Pseudo Adders (PA).
• Each PA block takes 3 input bits and produces 2 outputs: sum (S)
and carry (C).
• Carries are passed diagonally to the next higher bit position,
reflecting their higher weight.
• These PA blocks are connected in multiple levels, forming a tree-
like reduction, which continues until only two rows remain.
• A Carry Propagate Adder (CPA) adds the final two rows to give
the product P = A × B.
• This method is faster than an array multiplier, reducing delay to
logarithmic time.
Dadda multiplier

• The Dadda Dot Diagram is used to represents the reduction process of

partial products in a Dadda multiplier.
• The diagram shows partial product bits as black dots arranged in
columns (same weight).
• The goal is to compress each column's height step by step using Dadda’s
algorithm.
• Full adder group 3 dots into 2 (sum + carry), and half adders group 2
dots into 1.
• The process continues through multiple levels (lines) until only 2 rows of
dots remain.
• Finally, a carry propagate adder (e.g., ripple or carry-lookahead adder)
is used to get the final product.
• Compared to Wallace, Dadda uses fewer adders, making it more area-
efficient while maintaining high speed.
Thank you