CONTENTS

• Introduction
• Literature Survey
• Technical Aspects
• Applications/advantages/limitations
• Conclusion
• References

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 INTRODUCTION
With CMOS technology advancing to 5nm and beyond, FinFETs and Gate-All-
Around FETs (GAAFETs) have emerged as key transistor architectures.
FinFETs, known for their strong electrostatic control and mature
manufacturing processes, face limitations in scalability at advanced nodes.
GAAFETs, with gates surrounding the entire channel, offer improved short-
channel control, lower leakage, and better scalability—though at the cost of
increased fabrication complexity. As industry leaders like Intel, TSMC, and
Samsung transition to GAAFETs for future nodes, understanding the design,
operation, and challenges of both technologies is vital for driving the next era
of semiconductor scaling.

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 LITERATURE SURVEY
[1] From MOSFET to FinFET to GAAFET: The Evolution, Challenges, and Future Prospects

This paper discusses the evolution from MOSFETs to FinFETs, highlighting the improvements in

performance and scalability. It notes that as device sizes shrink below 5nm, FinFETs face limitations,

and GAAFETs, offering better gate control and 3D structuring, are poised to address these challenges

for the future of digital technologies.

[2] Stress-related Local Layout Effects in FinFET Technology

This study focuses on how fabrication-induced stresses impact the reliability and performance of

FinFETs. It emphasizes the importance of minimizing misalignments during manufacturing to

improve electrical characteristics and prepare for challenges in transitioning to GAAFETs.

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 LITERATURE SURVEY
[3] Introduction of Gate-All-Around FET (GAAFET)

This paper provides a detailed overview of GAAFETs, which offer superior electrostatic control, mitigate

short-channel effects, and improve performance, power efficiency, and area utilization compared to FinFETs.

It also discusses fabrication challenges and the need for optimal material selection.

[4] A New Revolution in Logic Silicon IC Technology: GAA FETs are Replacing FinFETs

This paper advocates for the shift from FinFETs to GAAFETs in logic silicon ICs due to their better

scalability, lower power consumption, and higher current drive. It also addresses the challenges in integrating

GAAFETs into existing processes and design adaptations, but views GAAFETs as the future of transistor

technology.

[5] Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors

This review explores recent progress in GAAFET technology, particularly the incorporation of negative

capacitance, which allows subthreshold swing below 60 mV/decade. This development reduces power

consumption while maintaining high performance, offering a solution for ultra-scaled nodes in modern

microprocessors.

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 Technical Aspects
1. Device Structures
• FinFET: Features a 3D fin-like channel wrapped by the gate on three sides. The fin
height and width are critical for performance tuning.
• GAAFET: Uses a stacked nanosheet or nanowire structure where the gate
completely surrounds the channel (hence "gate-all-around"), offering even better
electrostatic control.

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 2. Electrostatic Control
 FinFET: Good gate control but struggles with short-channel effects (SCEs) as
dimensions shrink below 5nm.
 GAAFET: Superior electrostatic control due to full gate wrap-around, effectively
suppressing SCEs, DIBL (Drain-Induced Barrier Lowering), and leakage currents.

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 3. Scalability
• FinFET: Scaling below 5nm is difficult due to physical limitations of fin pitch and gate
length.
• GAAFET: More scalable thanks to flexible nanosheet width tuning, allowing better
performance-area trade-offs and easier technology scaling below 3nm.

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 4. Performance and Power
• FinFET: Offers good performance-power efficiency but is nearing its limit in drive
current improvement and leakage suppression.
• GAAFET: Higher drive current and lower leakage; better suited for high-
performance and low-power applications.

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 5. Fabrication Complexity
• FinFET: Mature technology with well-established process flows, but sensitive to
fin height and spacing variations.
• GAAFET: More complex fabrication due to multilayer epitaxy and precise control
of nanosheet/nanowire dimensions and uniformity; selective etching is also more
challenging.

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 6. Variability and Reliability
• FinFET: Affected by stress, local layout effects, and fin misalignment which impact
variability and yield.
• GAAFET: Reduces variability due to improved electrostatics but introduces new
challenges like mechanical stress in stacked nanosheets and parasitic capacitance
management.

7. Design Considerations
• FinFET: Requires careful layout for optimal performance (e.g., fin quantization,
spacing rules).
• GAAFET: Offers greater design flexibility with adjustable channel width, enabling
easier performance tuning, but requires new design tools and models.

8. Future Enhancements
• FinFET: Limited further improvement possible; considered a transitional technology.
• GAAFET: Can be enhanced with negative capacitance, strained channels, or 2D
materials, making it a strong candidate for future logic and AI-centric nodes.

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 APPLICATIONS
Application FinFETs GAAFETs
Widely used in Targeted for 3nm and
smartphones (14nm– below with improved
1. Mobile Processors
5nm) for balanced power power efficiency and
and performance performance
Offers better scalability
2. High-Performance Used in CPUs/GPUs for
and drive current for
Computing (HPC) fast, efficient processing
next-gen HPC
Enhances edge AI with
3. AI & Machine Powers AI chips with
lower leakage and higher
Learning good energy efficiency
density
Ideal for ultra-low-
4. IoT & Low-Power Effective for energy-
power, compact IoT
Devices sensitive applications
systems
Enables reliable scaling
5. Advanced Node Limited below 5nm due
to 3nm and beyond with
Scaling to electrostatic issues
better control

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 CONCLUSION
 FinFETs: Enabled CMOS scaling to 5nm; now limited by electrostatic control,
tunneling, and density at <3nm
 GAAFETs: Gate-all-around architecture improves control, drive current, and density for
sub-3nm nodes
 Adoption:
• Samsung: MBCFET (3nm), TSMC: N2 (2nm), Intel: RibbonFET
• Applications: AI, HPC, quantum computing
• Next-gen Technologies:
• CFETs (vertical stacking)
• 2D materials (MoS₂, WS₂)
• Backside Power Delivery
• Conclusion: GAAFETs are critical for future scaling; balancing PPA and cost is key to
sustaining Moore’s Law

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 REFERENCES
[1] H. Duan, “From MOSFET to FinFET to GAAFET: The Evolution, Challenges, and Future Prospects,”
Applied and Computational Engineering, vol. 50, pp. 113–120, Mar. 2024.
[2] A. Rossoni, L. Colalongo, and Z. M. Kovacs-Vajna, “Stress-related Local Layout Effects in FinFET
Technology and Device Design Sensitivity,” IEEE Transactions on Semiconductor Manufacturing, vol. 38, no. 2,
pp. 123–130, Feb. 2025.
[3] C. Xie, Y. Zhang, K. Zhang, and L. Z.-R. Guo, “Introduction of Gate-All-Around FET (GAAFET),” Applied
and Computational Engineering, vol. 28, no. 1, pp. 164–175, Dec. 2023.
[4] S. V. Kalinin, D. I. Ostertak, D. A. Poteryaev, and M. A. Kuznetsov, “A New Revolution in Logic Silicon IC
Technology: GAA FETs are Replacing FinFETs,” in Proceedings of the 2023 IEEE XVI International Scientific
and Technical Conference Actual Problems of Electronics Instrument Engineering (APEIE), Novosibirsk, Russia,
2023, pp. 1–5, doi: 10.1109/APEIE59731.2023.10347677.
[5] L. Qin, C. Li, Y. Wei, G. Hu, J. Chen, Y. Li, C. Du, Z. Xu, X. Wang, and J. He, “Recent Developments in
Negative Capacitance Gate-All-Around Field Effect Transistors: A Review,” IEEE Access, vol. 11, pp. 14028–
14042, 2023, doi: 10.1109/ACCESS.2023.3243697.

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 ANY QUESTIONS ?

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 THANK YOU

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