Synchronous and Asynchronous
Memory Interface
Address
Memory read
CPU Memory write Memory Figure 4a. Synchronous
Memory Interface
Data
Address
Memory read
CPU Memory write Memory Figure 4b. Asynchronous
Memory Interface
Data
MFC
FUNCTIONAL UNITS IN COMPUTER
Memory
Input Output
Unit Unit
CPU Control Unit ALU
Figure 1. Control diagram
CPU-MEMORY COMMUNICATION
The CPU addresses the memory both for a memory
read operation and a write operation
Memory Read Operation
1. The CPU sends the address of the location
2. The CPU sends the memory read signal
3. On receiving the memory read signal, the
memory starts reading from the memory location
pointed by the address, the time taken for the
read operation is the access time.
4. After the access time, the memory puts the
content of the location on the data lines
Main Memory Contd
16 bits 32 bits
2 k locations 1 k locations
(a) 2048 X 16 (b) 1024 X 32
Figure 12 . Memory capacity and organisation
DEVICE INTERFACE SIGNALS
TYPES OF SIGNALS
There are 3 types of signals between a device
and a device controller:
Data
Control
Status
Data
Control signals
Controller Device
Status signals
Figure 4. Device interface signals
DEVICE INTERFACE
SIGNALS
Control signals are issued by the device
controller demanding certain actions by the
device e.g. RESET
Status signals are sent by the I/O device
reporting certain internal conditions to the
device controller e.g. ERROR, PAPER EMPTY
Data signal transfers data from the device
controller to the device.
Data signals may be unidirectional or bidirectional
Data signals may be sent serially (serial interface)
or in parallel (Parallel interface)
Direct Memory Access (DMA) CONTROLLER
DMA controller transfers data without the
intervention of the processors, but the
processor controls the data transfer
DMA controller contains an address unit that
generates an address and selects an I/O device
to transfer data. Figures 8 and 9 show the
block diagram of the DMA controller and the
working diagram of the DMA controller,
respectively.
ECE 3252
COMPUTER
ARCHITECTURE
Engr. Professor Alice
Oluwafunke Oke
Department of Computer Engineering, ACU, Oyo
DEVICE INTERFACE SIGNALS
TYPES OF SIGNALS
There are 3 types of signals between a device
and a device controller:
Data
Control
Status
Data
Control signals
Controller Device
Status signals
Figure 4. Device interface signals
CPU OPERATION Contd
Fetch phase: An
instruction is fetched
Fetch instruction
from memory
Execute phase: the
instruction is Execute instruction
analysed and
relevant operations
are performed
Figure 5. Instruction Cycle Phases
DEVICE CONTROLLER
A device controller communicates with a device
through the device interface
The device interface carries the signals between a
device controller and a device
Command
register
Device
CPU and System System Device interface
System interface interface Data buffer interface I/O device
memory logic logic
Status
register
Device controller
Figure 2. Device interface and system interface
CPU-MEMORY COMMUNICATION
Memory Write Operation
Address
Memory write
CPU Memory
Data
Figure 2. Memory Write Operation
Example
Example 1
A CPU has a 12-bit address for memory addressing:
(a) What is the memory addressability of the CPU?
(b) If the memory has a total of 16KB, what is the word
length of the memory?
Solution
No. of address bits = ?
Memory addressability = 2? =
Memory capacity = 16 KB
Word length = ?
FUNCTIONAL UNITS IN COMPUTER Contd
The input and output units are electromechanical
units consisting of both electronic circuits and
mechanical assemblies
The input and output units are known as peripheral
devices
A program is a sequence of instructions used for
solving a problem
Main Memory and Auxiliary Memory
The memory from which the CPU fetches the
instructions is the main memory or primary
memory.
To run a program, it must be brought into the
main memory
Program Memory Auxiliary
storage
Input Output
CPU
devices devices
Figure 10. Main and auxiliary memory
CPU-MEMORY COMMUNICATION
The CPU addresses the memory both for a memory
read operation and a write operation
Memory Read Operation
1. The CPU sends the address of the location
2. The CPU sends the memory read signal
3. On receiving the memory read signal, the
memory starts reading from the memory location
pointed by the address, the time taken for the
read operation is the access time.
4. After the access time, the memory puts the
content of the location on the data lines
DEVICE CONTROLLER Contd
Hard disk
controller
Memory
Optical
disk
controller
CPU
Magnetic
Tape
controller
System interface
Figure 3. Common system interface
The device controllers communicate with the
system using the system bus
Nowadays, most controllers have Direct Memory
Access to execute their task, this increases
FUNCTIONAL UNITS IN COMPUTER
The ALU and control unit have some temporary
storage units called registers, it is a fast memory
with a single location.
This registers store information such as: instruction,
data, address, etc.
The storage in registers has the advantage of fast
processing, because the CPU can read them quickly
compared to fetching them from external memory.
ALU and CU are the Central Processing Unit (CPU)
Memory and CPU consist of electronic circuits and
form the heart of the computer
Main Memory
A typical memory structure is depicted in Figure
11
Address
0000 1st location
0001 2nd location
0010 3rd location
0011 4th location
1111 Last location (16th)
Figure 11 . Main memory locations
Computer
COMMUNICATION
Memory Write Operation
1. The CPU sends the address of the location
2. The CPU sends the data to be written
3. The CPU sends the memory write signal
4. On receiving the memory write signal, the memory
starts writing operation in the location corresponding
to the address, till the access time is over, as in Figure
2
Communication Registers in Memory R/W Operations
The CPU puts the memory address in the Memory
Address Register (MAR)
The CPU stores the data in the Memory Buffer Register (MBR)
during a write operation, as shown in Figure 3, while
The memory stores data in the MBR during a read operation
CPU-MEMORY COMMUNICATION
Address
Memory read
CPU Memory
Data
Figure 1. Memory Read Operation
CPU OPERATION Contd
Fetch
Operation code Operand instruction
Decode
Figure [Link] format instruction
Fetch
Consider an ADD instruction Operands
whose instruction format is as
Do
shown addition
Store
ADD opcode I operand address II operand address Result
Figure 6b. ADD Instruction format Figure 6c. Instruction
Cycle steps
