WELCOME
Dear Students
1
LINEAR AND DIGITAL IC
APPLICATIONS
Dr. P. PADMAJA
Professor,ECE Dept
09/21/2025
CONTENTS
INTRODUCTION
Specifications and Applications of TTL-74XX & CMOS 40XX Series ICs
CodeConverters,
Decoders,
LED&LCDDecoderswithDrivers,
Encoders,
PriorityEncoders,
Multiplexers,
Demultiplexers,
PriorityGenerators/Checkers,
ParallelBinaryAdder/Subtractor,
MagnitudeComparators.
09/21/2025
DECODERS
09/21/2025
Decoder
Specification
Digital readouts on many digital
products often use LED seven-
segment displays.
Each digit is created by lighting the
appropriate segments. The segments
are labeled a,b,c,d,e,f,g
The decoder takes a BCD input and
outputs the correct code for the
seven-segment display.
9/15/09 - L12
Combinational Copyright 2009 - Joanne
Logic Design DeGroat, ECE, OSU 5
Specification
Input: A 4-bit binary value that is a
BCD coded input.
Outputs: 7 bits, a through g for
each of the segments of the display.
Operation: Decode the input to
activate the correct segments.
6
BCD TO SEVEN SEGMENT
Construct a truth table
7
Optimization
Create a K-map for each output and
get
A = A’C+A’BD+B’C’D’+AB’C’
B = A’B’+A’C’D’+A’CD+AB’C’
C = A’B+A’D+B’C’D’+AB’C’
D=
A’CD’+A’B’C+B’C’D’+AB’C’+A’BC’D
E = A’CD’+B’C’D’
F = A’BC’+A’C’D’+A’BD’+AB’C’
G = A’CD’+A’B’C+A’BC’+AB’C’
8
decoder
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Decoder
Accepts a value and decodes it
Output corresponds to value of n
inputs
Consists of:
Inputs (n)
Outputs (2n , numbered from 0 2n - 1)
Selectors / Enable (active high or active
low)
4-8. Decoders
The decoder is called n-to-m-line decoder,
where m≤2n .
the decoder is also used in conjunction with
other code converters such as a BCD-to-
seven_segment decoder.
3-to-8 line decoder: For each possible input
combination, there are seven outputs that
are equal to 0 and only one that is equal to
1.
12
2-to-4 Decoder
Decoder Expansion
Decoder expansion
Combine two or more small decoders
with enable inputs to form a larger
decoder
3-to-8-line decoder constructed from
two 2-to-4-line decoders
The MSB is connected to the enable inputs
if A2=0, upper is enabled; if A2=1, lower is
enabled.
3 to 8 decoder us
Combining two 2-4 decoders to form one 3-8 decoder using enable switch
The highest bit is used for the enables
Implementation of a Full Adder with a
Decoder
From table 4-4, we obtain the functions for the combinational
circuit in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
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How about 4-16 decoder
Use how many 3-8 decoder?
Use how many 2-4 decoder?
23
For active high output
Realization of multiple output function using
decoder
BCD-to-Seven-Segment Decoder
Specification
Digital readouts on many digital
products often use LED seven-
segment displays.
Each digit is created by lighting the
appropriate segments. The segments
are labeled a,b,c,d,e,f,g
The decoder takes a BCD input and
outputs the correct code for the
seven-segment display.
9/15/09 - L12
Combinational Copyright 2009 - Joanne
Logic Design DeGroat, ECE, OSU 31
Specification
Input: A 4-bit binary value that is a
BCD coded input.
Outputs: 7 bits, a through g for
each of the segments of the display.
Operation: Decode the input to
activate the correct segments.
9/15/09 - L12
Combinational Copyright 2009 - Joanne
Logic Design DeGroat, ECE, OSU 32
Formulation
Construct a truth table
9/15/09 - L12
Combinational Copyright 2009 - Joanne
Logic Design DeGroat, ECE, OSU 33
Optimization
Create a K-map for each output and
get
A = A’C+A’BD+B’C’D’+AB’C’
B = A’B’+A’C’D’+A’CD+AB’C’
C = A’B+A’D+B’C’D’+AB’C’
D=
A’CD’+A’B’C+B’C’D’+AB’C’+A’BC’D
E = A’CD’+B’C’D’
F = A’BC’+A’C’D’+A’BD’+AB’C’
G = A’CD’+A’B’C+A’BC’+AB’C’
36
Simple application
Implementation of a Full Adder with a
Decoder
From table 4-4, we obtain the functions for the combinational
circuit in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
39
4-9. Encoders
An encoder is the inverse operation of a decoder.
We can derive the Boolean functions by table 4-7
z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7
40
Encoders
Perform the inverse operation of a
decoder
2n (or less) input lines and n
output lines
Encoders
Encoders with OR gates
8 to 3 encoder
Encoders
Perform the inverse operation of a decoder
2n (or less) input lines and n output lines
Priority encoder
V=0no valid inputs
V=1valid inputs
X’s in output columns
represent
don’t-care conditions
X’s in the input columns are
useful for representing a
truth
table in condensed form.
Instead of listing all 16
minterms of four variables.
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Priority encoder
If two inputs are active simultaneously, the
output produces an undefined combination. We
can establish an input priority to ensure that
only one input is encoded.
Another ambiguity in the octal-to-binary
encoder is that an output with all 0’s is
generated when all the inputs are 0; the output
is the same as when D0 is equal to 1.
The discrepancy tables on Table 4-7 and Table
4-8 can resolve aforesaid condition by providing
one more output to indicate that at least one
input is equal to 1.
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