Introduction to

ARM Series and

Architecture
D.K.Magdum
Contents

 Introduction to ARM Cortex-M series processors

 ARM Cortex-M architecture overview and RISC design philosophy
 Architecture features
 Interrupt management
 Hardware Architecture: Memory Organization, I/O Configuration and
Port mapping
 Power Management and Low-Power Modes
 Development Tools.
Concept of ARM cortex M-series Microcontroller

 The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Limited.
 These cores are optimized for low-cost and energy-efficient integrated circuits, which have been embedded

in tens of billions of consumer devices.

 The Arm® Cortex®-M group of processor cores is a series of cores optimized for power efficiency and

deterministic operation.
 It is widely used in microcontrollers (MCUs) and can also be found embedded into multi-core

microprocessor

 The Cortex portfolio is split broadly into three main categories:

 • Cortex-A -- application processor cores for a performance-intensive systems

 • Cortex-R – high-performance cores for real-time applications
 • Cortex-M – microcontroller cores for a wide range of embedded applications.rs (MPUs).
 Industrial Automation: ARM Cortex-M4 is widely used in industrial automation systems, including programmable

logic controllers (PLCs), motor control, and robotics. The high-speed performance, real-time processing, and

extensive range of peripherals make it suitable for demanding industrial applications.

The RISC philosophy is implemented with four major design rules:

1. Instructions - RISC processors have a reduced number of

instruction classes.
• These classes provide simple operations that can each execute in a
single cycle.
• The compiler or programmer synthesizes complicated operations
(for example, a divide operation) by combining several simple
instructions.
• Each instruction is a fixed length to allow the pipeline to fetch
future instructions before decoding the current instruction.
• In contrast, in CISC
processors the instructions
are often of variable size
and take many cycles to
execute.

4
2. Pipelines -The processing of instructions is broken down into smaller
units that can be executed in parallel by pipelines.
• Ideally the pipeline advances by one step on each cycle for maximum
throughput.
• Instructions can be decoded in one pipeline stage.

5
Pipelines
3. Registers - RISC machines have a large general-
purpose register set.

• Registers act as the fast

local memory store for all
data processing operations.

ALWAYS THINK ABOUT

* CAPACITY
*COST
*SPEED

4. Load-store architecture - The processor operates on

data held in registers.
Separate load and store instructions transfer data between
the register bank and external memory.
Memory accesses are costly, so separating memory 7

accesses from data processing provides an advantage

• These design rules allow a RISC processor to be
simpler
• and thus the core can operate at higher clock
frequencies
In contrast,

• The traditional CISC processors are more complex

and operate at lower clock frequencies.

But the bottom line is……..

Over the course of two decades,

however, the distinction between RISC
and CISC has blurred as CISC processors 8

have implemented more RISC concepts.

STM32L476RG

 The STM32L476RG is a high-performance ultra-low-power

microcontroller from the STM32L4 family developed by
STMicroelectronics.
 It is built around the ARM Cortex-M4 core with Floating Point
Unit (FPU) and is designed for energy-efficient embedded systems.
 Features:
Architecture of STM32L476RG
Architectural Blocks
 ARM Cortex-M4 Core
 32-bit RISC processor with Harvard architecture.
 Operates at up to 80 MHz.
 Includes FPU (Floating Point Unit) for mathematical operations.
 Supports DSP instructions for digital signal processing.
 Handles interrupts using Nested Vector Interrupt Controller (NVIC).
 Memory Units
 Flash Memory (1 MB): Stores application code and constant data.
 SRAM (128 KB): Volatile memory for variable and stack data.
 EEPROM Emulation: Implemented in Flash for storing user configuration.
 Boot ROM: Contains the bootloader for device programming via USB/UART.
 Clock System (RCC – Reset and Clock Control)
 Manages system clock distribution.
 Internal Oscillators: HSI (16 MHz), MSI (multi-speed), LSI (low-speed).
 External Oscillators: HSE (up to 24 MHz), LSE (32.768 kHz).
 PLL (Phase Locked Loop): For generating high-speed system clocks.
 Power Management Unit (PMU)
 Provides ultra-low-power modes:
 Sleep, Stop 0, Stop 1, Stop 2
 Standby and Shutdown
 Supports voltage scaling and VBAT domain for RTC backup.
 Bus Matrix and Interconnects (AMBA AHB/APB)
 Uses AMBA (Advanced Microcontroller Bus Architecture):
 AHB: High-speed access (for DMA, core, and memory).
 APB1/APB2: For slower peripherals.
 Enables parallel access between core, memory, and peripherals.
 DMA Controller
 Direct Memory Access (DMA) with 16 channels.
 Allows data transfer between peripherals and memory without CPU load.
 Improves speed and efficiency of data handling.
 Interrupt System (NVIC)
 Handles 91 maskable interrupts.
 Provides preemption and priority control.
 Enables fast response for real-time applicatio
 Timers and Counters
 Advanced Timer (TIM1): For PWM and motor control.
 General-purpose Timers (TIM2–TIM5).
 Basic Timers (TIM6, TIM7): For DAC and internal timing.
 Watchdog Timers: For fault detection and system recovery.
 Communication Interfaces
 USART/UART (3x): For asynchronous serial communication.
 SPI (3x): Synchronous communication with sensors/memory.
 I2C (3x): Used in multi-master/slave configuration.
 USB 2.0 FS: Full-Speed USB device interface.
 CAN: Controller Area Network for automotive use.
 SDMMC: Interface for SD card storage.
 Analog Peripherals
 3 × 12-bit ADCs: Convert analog input to digital.
 2 × 12-bit DACs: Convert digital data to analog output.
 Op-Amps and Comparators: Signal conditioning and level detection.
 Internal Temperature Sensor: For thermal monitoring.
 GPIO – General Purpose I/Os
 Up to 81 configurable I/O pins.
 Each GPIO supports:
 Digital input/output
 Analog input
 Alternate function
 Interrupt triggering
 Used for LEDs, switches, displays, etc.
 Security and Safety Features
 CRC Generator: Ensures data integrity.
 AES 256-bit encryption and True Random Number Generator (TRNG): For
cryptographic applications.
 Independent Watchdog (IWDG) and Window Watchdog (WWDG).
 Debug and Programming Interfaces
 SWD (Serial Wire Debug) and JTAG interfaces for:
 Debugging during development.
 Flashing firmware to the device.
 Supported by STM32CubeIDE, Keil MDK, and ST-LINK.
Pin diagram
Nucleo Development Boards
Nucleo Board Block Diagram
Relevant Parts of Nucleo Board
Peripherals and GPIO Associated to
Arduino header
Peripherals and GPIOs associated to
Morpho headers
Memory mapped I/O and I/O mapped I/O
Memory Map
Interrupts and Exceptions Handling
 Interrupts and exceptions are asynchronous events that alter the program
flow.
 The CPU suspends the execution of the current task,saves its context (that
is, its stack pointer) and starts the execution of a routine designed to handle
the interrupting event.
 This routine is called Exception Handler in case of exceptions and Interrupt
Service Routine (ISR) in case of an interrupt.
 Interrupts are usually generated from on-chip peripherals (e.g., a timer) or
external inputs (e.g. a tactile switch connected to a GPIO), and in some
cases they can be triggered by software.
 Exceptions are, instead, related to software execution, and the CPU itself
can be a source of exceptions. These could be fault events such as an
attempt to access an invalid memory location, or events generated by the
Operating System, if any.
NVIC

 Both exceptions and interrupts are processed by a dedicated unit

called Nested Vectored Interrupt Controller (NVIC)
 The NVIC has the following features
 Flexible exception and interrupt management
 Nested exception/interrupt support
 Vectored exception/interrupt entry
 Interrupt masking
 Deterministic interrupt latency
 Relocationofexceptionhandlers
Power Modes