EEE3822 – Digital Systems
(Topic: Programmable Logic Devices)
Fakhrul Zaman Rokhani, PhD, PEng, PTech
Associate Professor
Dept. of Computer & Communication Systems Engineering, Faculty of
Engineering
System-on-Chip Research Center of Excellence (SoC-RCoE)
Malaysian Research Institute on Ageing (MyAgeingTM)
Halal Product Research Institute (HPRI)
Universiti Putra Malaysia
[email protected] Programmable Logic Devices
Programmable Logic
Devices
2
What Will We Learn in this Chapter?
• Introduction to design entries and abstraction levels
• Evolution of IC technologies
• Design methodologies
• Programmable Logic Devices (PLDs)
• Field Programmable Gate Array (FPGA)
3
Design Abstractions
English specification
Executable Throughput,
Increasing Physical info (& Design Cost)
behavior design time
program
Function units,
Sequential register-transfer
clock cycles
Increasing Functional info
machines
Literals,
logic
Logic gates logic depth
Transistors circuit Nanoseconds
Rectangles layout Microns
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Digital Hardware
• Logic circuits are implemented as integrated circuit
chips.
• How “complex” are these chips?
Year 2006 2007 2010
No. of transistors 2.4 billion 3 billion 6 billion
$100 $40
Smaller chips are less
expensive
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Moore’s Law
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The number of transistors on an integrated circuit will double every 18 months
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International Roadmap for Semiconductors
A sample of the International Technology Roadmap for Semiconductors.
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Design Approaches
Digital Circuit Implementation Approaches
Standard IC Full Custom Semicustom Programmable
PLD, CPLD
FPGA
Cell-based Array-based
Standard Cells Pre-diffused Pre-wired
Ma cro Cells
Compiled Cells (Gate Arrays)
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Implementation Spectrum
Single-
General-purpose
General, processor
ASIP purpose
processor
Customized,
providing improved: providing improved:
Flexibility Power efficiency
Maintainability Performance
NRE cost Size
Time- to-prototype Cost (high volume)
Time-to-market
Cost (low volume)
PLD Semi-custom Full-custom
Design Styles (1/2)
• Full-Custom ASICs
– Some (possibly all) logic cells are customized and all mask
layers are customized
• Semicustom ASICs
– All logic cells are predesigned (defined in cell library) and
some (possibly all) of the mask layers are customized
– Types:
Standard-cell based and Gate-array-based ASICs
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Design Styles (2/2)
• Programmable ASICs
– All logic cells are predesigned and
none of the mask layers are customized
– Types: PLD (Programmable Logic Device) and
FPGA (Field Programmable Gate Array)
– https://www.asicnorth.com/blog/asic-vs-fpga-difference/
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Full-Custom ASICs (1/3)
• Engineers design some or all of the logic cells, circuits,
or layout specifically for one ASIC
– Full-custom ICs are the most expensive
to manufacture and to design
– Manufacturing lead time (the time it takes just to make an
IC – not including design time) is typically 8 weeks
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Full-Custom ASICs (2/3)
• When does it make sense?
– there are no suitable existing cell libraries available
– existing logic cells are not fast enough
– logic cells are not small enough
– logic cells consume too much power
– ASIC is so specialized that
some circuits must be custom designed
• Trends: fewer and fewer full-custom ICs are being
designed (excluding mixed analog/digital ASICs)
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Full-Custom ASICs (3/3)
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Semi Custom
• Semi custom implementation does not require a complete run through
manufacturing process, which is expensive and time consuming.
• This comes at the expense of lower performance, lower integration
density, or higher power dissipation.
• https://semiengineering.com/knowledge_centers/eda-design/definitio
ns/ppa/
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Classification of Programmable Devices
• Based on Programming Technique
– Fuse-based (program-once)
– Non-volatile EPROM based
– RAM based
• Programmable Logic Style
– Array-Based
– Look-up Table
• Programmable Interconnect Style
– Channel-routing
– Mesh networks
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Look-up Table Based Logic Cell
In Out
Out 00 0
Memory 01 1
10 1
11 0
ln1 ln2
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What is a PLD? (1/2)
• A programmable logic device is a circuit which can be
configured by the user to perform a logic function.
• Most “standard” PLDs consist of an AND array followed by
an OR array, either (or both) of which is programmable.
• Inputs are fed into the AND array, which performs the
desired AND functions and generates product terms. The
product terms are then fed into the OR array. In the OR
array, the outputs of the various product terms are
combined to produce the desired outputs.
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What is a PLD? (2/2)
• PLDs
– standard ICs, available in standard configurations
– sold in high volume to many different customers
– PLDs may be configured or programmed to create
a part customized to specific application
• Characteristics
– no customized mask layers or logic cells
– fast design turnaround
– a single large block of programmable interconnect
– a matrix of logic macrocells that usually consists of programmable array logic
followed by a flip-flop or latch
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Array-Based Programmable Logic
I5 I4 I3 I2 I1 I0 Programmable
OR array I3 I2 I1 I0 Programmable
OR array I5 I4 I3 I2 I1 I0 Fixed OR array
Programmable AND array Fixed AND array Programmable AND array
O 3O 2O 1O 0 O 3O 2 O 1 O 0 O 3O 2O 1O 0
PLA PROM PAL
Indicates programmable connection
Indicates fixed connection
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Programming a PROM
1 X2 X1 X0
: programmed node
NA NA f 1 f 0
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Programmable Logic Arrays (PLAs)
• Any combinational logic function can be realized as a sum of
products.
• Idea: Build a large AND-OR array with lots of inputs and
product terms, and programmable connections.
– n inputs
• AND gates have 2n inputs -- true and complement of each variable.
– m outputs, driven by large OR gates
• Each AND gate is programmably connected to each output’s OR gate.
– p AND gates (p<=2n)
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Example: 4x3 PLA, 6 product terms
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PLA Compact representation
• Actually, closer to physical layout (“wired logic”).
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Some product terms
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PLA Electrical Design
• Wired-AND logic
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Programmable Array Logic (PALs) (1/2)
• PALs ==> programmable AND, fixed OR array
– Each AND gate is permanently connected to a certain OR gate.
• Example: PAL16L8
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Programmable Array Logic (PALs) (2/2)
• 10 primary inputs
• 8 outputs, with 7 ANDs per output
• 1 AND for 3-state enable
• 6 outputs available as inputs
– more inputs, at expense of outputs
• Note inversion on outputs
– output is complement of sum-of-
products
– newer PALs have selectable inversion
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Sequential PALs
• 16R8
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One output of 16R8
• 8 product terms to D input of flip-flop
– positive edge triggered, common clock for all
• Q output is fed back into AND array
– needed for state machines and other applications
• Common 3-state enable for all output pins
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PAL Compact Representation
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Field-Programmable Gate Arrays (FPGA)
• FPGAs use a grid of logic gates, similar to that of an ordinary gate array, but the
programming is done by the customer.
• The term “field-programmable” means the array is done outside the factory, or “in
the field”.
• Characteristics
– none of mask layers are customized
– a method for programming basic cells
and the interconnect
– the core is regular array
of programmable basic logic cells
(combinational + sequential)
– a matrix of programmable interconnect
that surrounds the basic cells
– programmable I/O cells around the core
– design turnaround is a few hours
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FPGA market share by company
Programmable Logic 1998 Market Share
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Field-Programmable Gate Arrays (FPGAs) (1/4)
“balls”
General FPGA chip architecture
Logic
Array
Block
(LAB)
package
Pins /
IO pad
Mini printed
circuit board
(pcb)
Programmable interconnect
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Field-Programmable Gate Arrays (FPGAs) (2/4)
Logic element
(implements a truth
table)
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Field-Programmable Gate Arrays (FPGAs) (3/4)
programmable switch
1/0 - memory cell
(storage)
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Field-Programmable Gate Arrays (FPGAs) (4/4)
• Logic Element (LE)
– Contains storage called lookup table
(LUT); the LUT is used to store a truth
table
– Eg. 2-input LUT (NOR)
0
X1 f
0
f
X2 0
X1
X2
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Logic Element
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Recall: A Bigger Memory Array (4 locations X 3 bits)
Addr[1:0]
Di[2] Di[1] Di[0]
WE
Address Decoder
Multiplexer D[2] D[1] D[0]
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Memory-Based Lookup Table Example
• Memory arrays can also perform Boolean Logic functions
– 2N-location M-bit memory can perform any N-input, M-output function
– Lookup Table (LUT): Memory array used to perform logic functions
– Each address: row in truth table; each data bit: corresponding output value
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Lookup Tables (LUTs)
• LUTs are commonly used in FPGAs
– To enable programmable/reconfigurable logic functions
– To enable easy integration of combinational and sequential logic
Read H&H Chapter 5.6.2 41
Software Tools
• FPGA Computer Aided Design (CAD) flow has five major steps:
1. Optimize logic functions (like our algebraic manipulation)
2. Map the function from (1) into LUTs
(eg. 6-input AND, it might take 2 LUTs)
3. Place each LUT on the FPGA chip. Fitting
4. Choose wires
5. Produce FPGA programming file
• 85k Logic Elements (LE) in FPGA (DE1-SoC) – circuit has 85k LUTs
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The Fitter’s Job
• Partition logic functions into LEs
• Arrange the LEs
• Interconnect the LEs
• Minimize the number of LEs used
• Minimize the size and delay of interconnect used
• Work with constraints
– “Locked” I/O pins
– Critical-path delays
– Setup and hold times of storage elements
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Design Tools – Quartus Prime
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Configuring the FPGA
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Configuring the routing in an FPGA
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DE1-SoC Board
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DE1-SoC Board – Block Diagram
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Architecture Cyclone-V SoC
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Features of Cyclone V FPGA
• Cyclone V FPGA, 5CSEMA5F31C6N
• 85K LE (logic elements), 32K ALM (Adaptive logic module)
• 128K flip-flops
• 3970 Kbits embedded memory
• 87 DSP block
• 174 multiplier 18x18
• GPIO: 288 FPGA, 181 HPS
• PLLs : 6x FPGA, 3x HPS
• Hard memory controllers : 1x FPGA
Cyclone V Adaptive Logic Module (ALM)
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Cyclone V Chip-level Structure
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Problems common to CPLDs and FPGAs
• Pin locking
– Small changes, and certainly large ones, can cause the fitter to pick a different
allocation of I/O blocks and pinout.
– Locking too early may make the resulting circuit slower or not fit at all.
• Running out of resources
– Design may “blow up” if it doesn’t all fit on a single device.
– On-chip interconnect resources are much richer than off-chip; e.g., barrel-
shifter example.
– Larger devices are exponentially more expensive.
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Terima Kasih | Thank You
