Module-2

Sequential Circuits
 Sequential Logic
• The digital circuits considered thus far have been combinational, i.e., the
outputs at any instant of time are entirely dependent upon the inputs
present at that time.
• Although every digital system is likely to have combinational circuits,
most systems encountered in practice also include memory elements,
which require that the system be described in terms of sequential logic.
 Sequential Logic
• A block diagram of a sequential circuit is shown in Fig. 6-1. It consists of a
combinational circuit to which memory elements are connected to form a
feedback path.
• The memory elements are devices capable of storing binary information
within them. The binary information stored in the memory elements at any
given time defines the state of the sequential circuit.
• The sequential circuit receives binary information from external
inputs. These inputs, together with the present state of the memory
elements, determine the binary value al the output terminals.
• They also determine the condition for changing the state in the memory
elements.
• The block diagram demonstrates that the external outputs in a sequential
circuit are a function not only of external inputs but also of the present
state of the memory elements.
• The next state of the memory elements is also a function of external inputs
and the present state. Thus, a sequential circuit is specified by time
sequence of inputs, outputs, and internal states.
 Sequential Logic
• There are two main types of sequential circuits. Their
classification depends on the timing of their signals.
• A synchronous sequential circuit is a system whose behavior
can be defined from the knowledge of its signals at discrete
instants of time.
• The behavior of an asynchronous sequential circuit depends
upon the order in which its input signals change and can be
affected at any instant of time.
Flip-Flops
• These circuits are binary cells capable of storing one bit of
information. A flip-flop circuit has two outputs, one or the
normal value and one for the complement value of the bit
stored in it.
 Sequential Logic
. Basic Flip-Flop Circuit--- Input is driven by output
 Sequential Logic
• To analyze the operation of the circuit of Fig, 6-2, we must remember that
the output of a NOR gate is 0 if any input is 1, and that the output is 1 only
when all inputs are 0. As a starting point, assume that the set input is 1 and
the reset input is 0. Since gate 2 has an input of 1, its output Q′ must be 0,
which puts both inputs of gate 1 at 0, so that output Q is 1. When the set
input is returned to 0, the outputs remain the same, because output Q
remains a 1, leaving one input of gate 2 at 1.
• That causes output Q′ to stay at 0, which leaves both inputs of gate
number 1 at 0, so that output Q is a 1. In the same manner it is possible to
show that a 1 in the reset input changes output Q to 0 and Q′ to 1. When
the reset input returns to 0, the outputs do not change.
• When a 1 is applied to both the set and the reset inputs, both Q and Q′
outputs go to 0. This condition violates the fact that outputs Q and Q′
are the complements of each other.
• In normal operation this condition must be avoided by making sure
that l’s are not applied to both inputs simultaneously.
 Sequential Logic
• Using NAND

intermediate

TT of NAND
 Sequential Logic
Clocked RS Flip—Flop-
• The outputs of the two AND gates remain at 0 as long as the
clock pulse (abbreviated CP) is 0, regardless of the S and R
input values.
• When the clock pulse goes to 1, information from the S and R
inputs is allowed to reach the basic flip-flop.
• The set state is reached with S = 1, R = 0. and CP = 1. To
change to the clear state, the inputs must be S = 0, R = 1, and
CP = 1.
• With both S = 1 and R = 1, the occurrence of a clock pulse
causes both outputs to momentarily go to 0. When the pulse
is removed, the state of the flip-flop is indeterminate, i.e.,
either state may result, depending on whether the set or the
reset input of the basic flip-flop remains a 1 longer before the
transition to 0 at the end of the pulse.
 Sequential Logic
Clocked RS Flip—Flop-
 Sequential Logic
D Flip Flop-D Flip Flop- NAND gates 1 and 2 form a basic flip-flop and gates 3
and 4 modify it into a clocked RS flip-flop. The D input goes directly to the
S input, and its complement, through gate 5, is applied to the R input. The
D flip-flop receives the designation from its ability to transfer “data” into a
flip-flop.

TT D ff
 Sequential Logic
• Clocked JK Flip Flop-A JK flip-flop is a refinement of the RS flip-flop in
that the indeterminate state of the RS type is defined in the JK type. Inputs
J and K behave like inputs S and R to set and clear the flip-flop. When
inputs are applied to both J and K simultaneously, the flip-flop switches to
its complement state, that is, if Q = 1, it switches to Q = 0, and vice versa.
• Note- that because of the feedback connection in the JK flip-flop, a CP
signal which remains 1 (while J = K = 1) after the outputs have been
complemented once will cause repeated and continuous transitions of
the outputs.(that is, if Q = 1, it switches to Q = 0, and vice versa.)
• To avoid this undesirable operation, the clock pulses must have a time
duration which is shorter than the propagation delay through the flip-
flop.
• This is a restrictive requirement, since the operation of the circuit
depends on the width of the pulses.
• For this reason, JK flip-flops are never constructed as shown in Fig, 6-
6(a). The restriction on the pulse width can be eliminated with a master-
slave or edge-triggered construction
 Sequential Logic
Clocked JK Flip Flop-

Q(t+1)=QK’+ Q’J
 Sequential Logic

• JK flip-flops- since the operation of the circuit

depends on the width of the pulses.
• For this reason, JK flip-flops are never constructed
as shown in Fig, 6-6(a). The restriction on the pulse
width can be eliminated with a master-slave or
edge-triggered construction

How we can achieve toggling?

1) Using edge triggering
2) Using Master-slave ff
 Sequential Logic
Clocked T Flip Flop-
• The T flip-flop is a single-input version of the JK flip-flop. As shown in
Fig. 6-7(a), the T flip-flop is obtained from a JK type if both inputs are tied
together. The designation T comes from the ability of the flip-flop to
“toggle,” or change state.
• Regardless of the present state of the flipflop, it assumes the
complement state when the clock pulse occurs while input T is logic-1.
 Sequential Logic
• Clocked T Flip Flop-

Toggle
 Triggering of Flip-flops
• The state of a flip-flop is switched by a momentary change in the input
signal. This momentary change is called a trigger and the transition it
causes is said to trigger the flip-flop.
• Clocked flip-flops are triggered by pulses. A pulse starts from an initial
value of 0, goes momentarily to 1, and after a short time,
 Triggering of Flip-flops
• The state of a flip-flop is switched by a momentary change in the input
signal. This momentary change is called a trigger and the transition it
causes is said to trigger the flip-flop.
• Clocked flip-flops are triggered by pulses. A pulse starts from an initial
value of 0, goes momentarily to 1, and after a short time,
• A clock pulse may be either positive or negative. A positive clock source
remains at 0 during the interval between pulses and goes to 1 during the
occurrence of a pulse.
• The pulse goes through two signal transitions; from 0 to 1 and the return
from 1 to 0. As shown in Fig. 6-8, the positive transition is defined as the
positive edge and the negative transition as the negative edge.
• This definition applies also to negative pulses. returns to its initial 0 value.
 Master-Slave Flip-Flop
• A master-slave flip-flop is constructed from two separate flip-flops. One
circuit serves as a master and the other as a slave, and the overall circuit is
referred to as a master-stave flip-flop.
• It consists of a master flip-flop, slave flip-flop, and an inverter. When clock
pulse CP is 0, the output of the inverter is 1. Since the clock input of the
slave is 1, the flip-flop is enabled and output Q is equal to Y, while Q′ is
equal to Y′.
• The master flip-flop is disabled because CP = 0. When the pulse becomes
1, the information then at the external R and S inputs is transmitted to the
master flip-flop.
• The slave flip-flop, however, is isolated as long as the pulse is at its 1 level,
because the output of the inverter is 0.
• When the pulse returns to 0, the master flip-flop is isolated, which prevents
the external inputs from affecting it. The slave flip-flop then goes to the
same state as the master flip-flop.
Master-Slave Flip-Flop
 Master-Slave Flip-Flop
• Master-slave JK flip-flop constructed with NAND gates is shown in Fig. 6-
11. It consists of two flip-flops; gates 1 through 4 form the master flip-flop,
and gates 5 through 8 form the slave flip-flop. The information present at
the J and K inputs is transmitted to the master flip-flop on the positive edge
of a clock pulse and is held there until the negative edge of the clock pulse
occurs, after which it is allowed to pass through to the slave flip-flop.
 Master-Slave Flip-Flop
• Master-slave JK flip-flop constructed with NAND gates is shown in Fig. 6-
11. It consists of two flip-flops; gates 1 through 4 form the master flip-flop,
and gates 5 through 8 form the slave flip-flop.
• The information present at the J and K inputs is transmitted to the master
flip-flop on the positive edge of a clock pulse and is held there until the
negative edge of the clock pulse occurs, after which it is allowed to pass
through to the slave flip-flop.
• The clock input is normally 0, which keeps the outputs of gates 1 and 2 at
the 1 level. This prevents the J and K inputs from affecting the master flip-
flop. The slave flip-flop is a clocked RS type, with the master flip-flop
supplying the inputs and the clock input being inverted by gate 9.
 Master-Slave Flip-Flop
• When the clock is 0, the output of gate 9 is 1, so that output Q is equal to
Y. and Q′ is equal to Y′. When the positive edge of a clock pulse occurs, the
master flip-flop is affected and may switch states.
• The slave flip-flop is isolated as long as the clock is at the 1 level, because
the output of gate 9 provides a 1 to both inputs of the NAND basic
• flip-flop of gates 7 and 8. When the clock input returns to 0, the master
flip-flop is isolated from the J and K inputs and the slave flip-flop goes to
the same state as the master flip-flop.
 Master-Slave Flip-Flop
Direct input
• Flip-flops available in IC packages sometimes provide special inputs for
setting or clearing the flip-flop asynchronously. These inputs are usually
called direct preset and direct clear.

The direct clear input also has a small circle to

indicate that, normally, this input must be
maintained at 1.
 Master-Slave Flip-Flop
Direct input
• The graphic symbol of a master-slave flip-flop with direct clear is shown in
Fig. 6-14.
• The clock or CP input has a circle under the small triangle to indicate
that the outputs change during the negative transition of the pulse. (The
absence of the small circle would indicate a positive edge- triggered flip-
flop.)
• The direct clear input also has a small circle to indicate that, normally, this
input must be maintained at 1.
• The outputs do not change if J = K = 0. The flip-flop toggles or
complements when J = K = 1.
 Master-Slave Flip-Flop
Direct input
• If the clear input is maintained at 0, the flip-flop remains cleared,
regardless of the other inputs or the clock pulse. The function table
specifies the circuit operation.
• The X’s are don’t-care conditions which indicate that a 0 in the direct clear
input disables all other inputs. Only when the clear input is 1 would a
negative transition of the clock have an effect on the outputs.
• The outputs do not change if J = K = 0. The flip-flop toggles or
complements when J = K = 1.
• Some flip-flops may also have a direct preset input which sets the output Q
to 1 (and Q′ to 0) asynchronously.
 Edge-Triggered Flip-Flop
Operation of the D-type edge-triggered flip-flop

• Another type of flip-flop that synchronizes the state changes during a clock
pulse transition is the edge-triggered flip-flop.

•when input clock pulse makes a positive-

going transition, value of D- transferred to Q.
•Changes in D when CP is maintained at a
steady 1 value do not affect Q.
•negative pulse transition does not affect the
output, nor does it when CP = 0.
•Hence, the edge-triggered flip-flop eliminates
any feedback problems in sequential circuits
just as master-slave flip-flop does.