ARM

ARM
• The ARM processor, like all RISC processors, uses a load-store
architecture.
• There are no data processing instructions that directly manipulate
data in memory. Thus, data processing is carried out solely in
registers.
Cont…
• Data items are placed in the register file—a storage bank made up of
32-bit registers.
• the ARM core is a 32-bit processor, most instructions treat the
registers as holding signed or unsigned 32-bit values. The sign extend
hardware converts signed 8-bit and 16-bit numbers to 32-bit values as
they are read from memory and placed in a register.
• ARM instructions typically have two source registers, Rn and Rm, and
a single result or destination register, Rd. Source operands are read
from the register file using the internal buses A and B, respectively.
Cont…
• The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the
register values Rn and Rm from the A and B buses and computes a result. Data
processing instructions write the result in Rd directly to the register file. Load
and store instructions use the ALU to generate an address to be held in the
address register and broadcast on the Address bus.
• Rm alternatively can be preprocessed in the barrel shifter before it enters the
ALU. Together the barrel shifter and ALU can calculate a wide range of
expressions and addresses.
• After passing through the functional units, the result in Rd is written back to the
register file using the Result bus. For load and store instructions the
incrementer updates the address register before the core reads or writes the
next register value from or to the next sequential memory location.
Registers
• General-purpose registers hold either data or an address.
• The processor can operate in seven different modes.
• All the registers shown are 32 bits in size.
• There are up to 18 active registers:
• 16 data registers and 2 processor status registers.
• The data registers are visible to the programmer as r0 to r15.
Cont…
• Register r13 is traditionally used as the stack pointer (sp) and stores
the head of the stack in the current processor mode.
• Register r14 is called the link register (lr) and is where the core puts
the return address whenever it calls a subroutine.
• Register r15 is the program counter (pc) and contains the address of
the next instruction to be fetched by the processor.
• In addition to the 16 data registers, there are two program status
registers: cpsr and spsr
Current Program Status Register
• The cpsr is divided into four fields, each 8 bits wide: flags, status,
extension, and control.
• The control field contains the processor mode, state, and interrupt
mask bits. The flags field contains the condition flags.
Processor Mode
• A privileged mode allows full read-write access to the cpsr.
Conversely, a nonprivileged mode only allows read access to the
control field in the cpsr but still allows read-write access to the
condition flags.
• There are seven processor modes in total: six privileged modes
(abort, fast interrupt request, interrupt request, supervisor, system,
and undefined) and one nonprivileged mode (user).
Banked Registers
• Every processor mode except user mode can change mode by writing
directly to the mode bits of the cpsr. All processor modes except
system mode have a set of associated banked registers that are a
subset of the main 16 registers. A banked register maps one-toone
onto a user mode register. If you change processor mode, a banked
register from the new mode will replace an existing register.
• The following exceptions and interrupts cause a mode change: reset,
interrupt request, fast interrupt request, software interrupt, data
abort, prefetch abort, and undefined instruction. Exceptions and
interrupts suspend the normal execution of sequential instructions
and jump to a specific location.
• The core changing from user mode to interrupt request mode, which
happens when an interrupt request occurs due to an external device
raising an interrupt to the processor core. This change causes user registers
r13 and r14 to be banked. The user registers are replaced with registers
r13_irq and r14_irq, respectively. Note r14_irq contains the return address
and r13_irq contains the stack pointer for interrupt request mode.
• a new register appearing in interrupt request mode: the saved program
status register (spsr), which stores the previous mode’s cpsr. You can see in
the diagram the cpsr being copied into spsr_irq. To return back to user
mode, a special return instruction is used that instructs the core to restore
the original cpsr from the spsr_irq and bank in the user registers r13 and
r14
Mode
• When power is applied to the core, it starts in supervisor mode, which
is privileged. Starting in a privileged mode is useful since initialization
code can use full access to the cpsr to set up the stacks for each of the
other modes.
State and Instruction Sets
• The state of the core determines which instruction set is being
executed. There are three instruction sets: ARM, Thumb, and Jazelle.

state

ARM Thumb Jazelle

Cont..
Cont…
• Interrupt masks are used to stop specific interrupt requests from
interrupting the processor. There are two interrupt request levels
available on the ARM processor core—interrupt request (IRQ) and
fast interrupt request (FIQ).
• The cpsr has two interrupt mask bits, 7 and 6 (or I and F), which
control the masking of IRQ and FIQ, respectively. The I bit masks IRQ
when set to binary 1, and similarly the F bit masks FIQ when set to
binary 1.
Cont…
Cont…
• With processor cores that include the DSP extensions, the Q bit
indicates if an overflow or saturation has occurred in an enhanced
DSP instruction. The flag is “sticky” in the sense that the hardware
only sets this flag. To clear the flag you need to write to the cpsr
directly.
• In Jazelle-enabled processors, the J bit reflects the state of the core; if
it is set, the core is in Jazelle state. The J bit is not generally usable and
is only available on some processor cores. To take advantage of
Jazelle, extra software has to be licensed from both ARM Limited and
Sun Microsystems. Most ARM instructions can be executed
conditionally on the value of the condition flags.
Condition
Pipeline

ARM9

ARM10
Vector table