Tutorial – 1
Show the block diagram of the hardware that
implements the following register transfer
statement
𝑦𝑇2:𝑅2←𝑅1,𝑅1←𝑅2
Show the block diagram of the hardware that
implements the following register transfer
statement
Solution
Represent the following conditional control
statement by two register transfer statements with
control functions
Represent the following conditional control
statement by two register transfer statements with
control functions
Solution
A digital computer has common bus
system for 16 registers of 32 bits
each
The bus is constructed with multiplexers
How many selection inputs are there in each multiplexer?
What size of multiplexers are needed?
How many multiplexers are there in the bus
A digital computer has common bus
system for 16 registers of 32 bits
each
Solution
The bus is constructed with multiplexers
How many selection inputs are there in each multiplexer? (4 Select Lines)
What size of multiplexers are needed? (16:1 MUX)
How many multiplexers are there in the bus? (32 multiplexer)
The following transfer statements specify a
memory. Explain the memory operation in each
case
The following transfer statements specify a
memory. Explain the memory operation in each
case
Solution
Read memory word specified by the address in AR into register R2
Write content of register R3 into the memory word specified by the address
in AR
Read memory word specified by the address in R5 and transfer content to R5
(destroys previous value)
Draw the block diagram for the hardware
that implements the following statements:
Where AR and BR are two n-bit registers and x, y and z are control
variables. Include the logic gates for the control function.
Draw the block diagram for the hardware
that implements the following statements:
Where AR and BR are two n-bit registers and x, y and z are control
variables. Include the logic gates for the control function.
Solution
Show the hardware that implements the
following statement. Include the logic gates for
the control function and a block diagram for the
binary counter with the count enable input
Show the hardware that implements the
following statement. Include the logic gates for
the control function and a block diagram for the
binary counter with the count enable input
Solution
Tutorial – 2
The output of four register (R0,R1,R2 and R3)
are connected through 4 to 1 line Multiplexers to
the inputs of the fifth Register (R5)
Each register is eight bits long. The required transfers are dictated by
four timing variables T0 through T3 as follows:
The timing variables are mutually exclusive, which means that only one
variable is equal to 1 at any given time, while the other three are equal to
0. Draw a block diagram showing the hardware implementation of the
register transfers. Include the connections necessary from the four timing
variables to the selection inputs of the multiplexers and to the load input of
register R5
Solution
The adder-subtractor circuit has the following values for
the input mode ‘M’ and data inputs ‘A’ and ‘B’. In each
case, determine the values of the outputs: S3, S2, S1,
S0 and C4
M A B
0 0111 0110
0 1000 1001
1 1100 1000
1 0101 1010
1 0000 0001
The adder-subtractor circuit has the following values for
the input mode ‘M’ and data inputs ‘A’ and ‘B’. In each
case, determine the values of the outputs: S3, S2, S1,
S0 and C4
Solution
M A B SUM C4
0 0111 0110 1101 0 7+6=13
0 1000 1001 0001 1 8+9=17
1 1100 1000 0100 1 12-8=4
1 0101 1010 1011 0 5-10=-5(2’s complement)
1 0000 0001 1111 0 0-1=-1(2’s complement)
Design a 4-bit combinational circuit
decrementer using four full adder circuit
Design a 4-bit combinational circuit
decrementer using four full adder circuit
Solution
Assume the 4-bit arithmetic circuit is enclosed in
one IC package. Show the connections among two
such IC’s to form an 8-bit arithmetic circuit
S1
S0
A0 X0 C0
S1 D0
B0
S0
Y0 FAC1
0
1 4x1
2
3 MUX
A1 X1 C1
S1 D1
B1
S0
Y1 FAC2
0
1 4x1
2
3 MUX
A2 X2 C2
S1 D2
B2
S0
Y2 FAC3
0
1 4x1
2
3 MUX
A3 X3 C3
S1 D3
B3
S0
Y3 FAC4
0
1 4x1
2
3 MUX Cout
0 1
Solution
Register A holds the 8-bit binary 1101 1001. Determine
the ‘B’ operand and the logic microoperation to be
performed in order to change the value in ‘A’ to
A. 0110 1101
B. 1111 1101
Register A holds the 8-bit binary 1101 1001. Determine
the ‘B’ operand and the logic microoperation to be
performed in order to change the value in ‘A’ to
A. 0110 1101
B. 1111 1101
Tutorial – 3
The 8-bit register AR, BR, CR and DR
initially have the following values
AR = 1111 0010
BR = 1111 1111
CR = 1011 1001
DR = 1110 1010
Determine the 8-bit value in each register after the execution of
the following sequence of micro-operations
Add BR to AR
AND DR to CR, increment BR
Subtract CR from AR
The 8-bit register AR, BR, CR and DR
initially have the following values
An 8-bit register contains the binary value 1001 1100.
What is the register value after an arithmetic shift right?
Starting from the initial number 1001 1100. Determine
the register value after an arithmetic shift left and state
whether there is an overflow.
An 8-bit register contains the binary value 1001 1100.
What is the register value after an arithmetic shift right?
Starting from the initial number 1001 1100. Determine
the register value after an arithmetic shift left and state
whether there is an overflow.
Solution
Starting from an initial value of R=1101 1101, determine the
sequence of binary value in R after a logical shift-left, followed by
circular shift right, followed by a logical shift right and a circular
shift left
Starting from an initial value of R=1101 1101, determine the
sequence of binary value in R after a logical shift-left, followed by
circular shift right, followed by a logical shift right and a circular
shift left
Solution
Tutorial – 4
What is the value of output ‘H’, if
input ‘A’ is 1001, S=1, IR =1, IL = 0
Serial Input IR Serial Input IL
A0A1 A2 A3
Select
0 for shift right
S 1 0 S 1 0 S 1 0 S 1 0
1 for shift left
MUX MUX MUX MUX
H0 H1 H2 H3
What is the value of output ‘H’, if
input ‘A’ is 1001, S=1, IR =1, IL = 0
Serial Input IR Serial Input IL
A0A1 A2 A3
Select
0 for shift right
S 1 0 S 1 0 S 1 0 S 1 0
1 for shift left
MUX MUX MUX MUX
H0 H1 H2 H3
What is wrong with the following
register transfer statements?
What is wrong with the following
register transfer statements?
A.
Cannot complement and increment the same register at the same time.
Cannot transfer two different values (R2 and R3) to the same register (R1)
at the same time.
Cannot transfer a new value into a register (PC) and increment the original
value by one at the same time.
Tutorial – 5
Design an arithmetic circuit with one selection variable ‘S’ and two n-
bit data inputs ‘A’ and ‘B’. The circuit generates the following four
arithmetic operations in conjunction with the input carry C in. Draw the
logic diagram for the first two stages
S Cin = 0 Cin = 1
0 D =A + B (add) D = A + 1 (increment)
1 D = A – 1 (decrement) D =A + B’ + 1(subtract)
Solution
S Cin = 0 Cin = 1
0 D =A + B (add) D = A + 1 (increment)
1 D = A – 1 (decrement) D =A + B’ + 1(subtract)
A computer uses a memory unit with 256K
words of 32 bits each. A binary instruction code
is stored in one word of memory. The instruction
has four parts: an indirect bit, an operation
code, a register code part to specify one of 64
registers and an address part.
How many bits are there in the operation code, the register code part
and the address part?
Draw the instruction word format and indicate the number of bits in
each part.
How many bits are there in the data and address inputs of the memory?
How many bits are there in the operation code, the register code part
and the address part?
Draw the instruction word format and indicate the number of bits in
each part.
How many bits are there in the data and address inputs of the memory?
What is the difference between direct and an indirect address
instruction? How many references to memory are needed for each
type of instruction to bring an operand into a processor register
What is the difference between direct and an indirect address
instruction? How many references to memory are needed for each
type of instruction to bring an operand into a processor register
The following control inputs are active in the bus
system. For each case, specify the Register Transfer
that will be executed during the next clock transition
S2 S1 S0 LD of Register Memory Adder
1 1 1 IR Read -
1 1 0 PC - -
1 0 0 DR Write -
0 0 0 Ac - Add
Solution
S2 S1 S0 LD of Register Memory Adder
1 1 1 IR Read -
1 1 0 PC - -
1 0 0 DR Write -
0 0 0 Ac - Add
The following register transfer are to be executed
in the system. For each transfer specify
The binary value that must be applied to the select inputs (S2, S1, S0)
The register whose LD control input must be active (if any)
A memory read or write operation (if needed)
The operation in the adder and logic circuit (if any)
The following register transfer are to be executed
in the system. For each transfer specify
Explain why each of the following microoperation cannot be
executed during a single clock pulse in the system. Specify a
sequence of microoperation that will perform the operation
Solution
Consider the instruction formats of the basic computer. For each of
the following 16-bit instructions, give the equivalent four digit Hexa-
decimal code and explain what that instruction is going to perform
0001 0000 0010 0100
1011 0001 0010 0100
0111 0000 0010 0000
Symbol Hexadecimal Code (I = Hexadecimal Code (I Description
0) = 1)
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC is positive
SNA 7008 Skip next instruction if AC is negative
SZA 7004 Skip next instruction if AC is zero
SZE 7002 Skip next instruction if E is zero
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
Solution
0001 0000 0010 0100
1011 0001 0010 0100
0111 0000 0010 0000
What are the two instructions needed in the
basic computer in order to set “E” F/F to 1?
What are the two instructions needed in the
basic computer in order to set “E” F/F to 1?
CLE – Clear E
CME – Compliment E
Draw a timing diagram, assuming that SC is
cleared to 0 at time T3 if control signal C7 is active
C7 is activated with the positive clock transition associated with T1
Solution
C7 is activated with the positive clock transition associated with T1
The content of AC in the basic computer is Hexadecimal A937 and the initial value
of E is 1. Determine the contents of AC, E, PC, AR and IR in Hexadecimal after the
execution of the CLA instruction. Repeat 11 more times, starting from each one of
the Register-Reference Instructions. The Initial value of PC is Hexadecimal 021
Solution
Initial E – 1, AC – A937, PC – 021
An instruction at address 021 in the basic computer has I=0, an operation code of the AND
instruction and an address part equal to 083 (Hexadecimal). The memory word at address 083
contains and operand B8F2 and content of AC is A937. What will the content of register PC, AR, DR,
AC and IR.
Repeat the problem six more times starting with the operation code of another memory reference
instruction. ]
Solution
Initial PC – 021, AC – A937
Show the contents in Hexadecimal of registers PC, AR, DR, IR
and SC of the basic computer when an ISZ indirect instruction
is fetched from the memory and executed.
Initially PC = 7FF, the content of memory at address 7FF is EA9F. The
content of the
Tutorial
Q1:A bus organised CPU has 16 registers with 32 bits in each, an ALU
and a destination decoder.
A. How many multiplexers are there in the A bus and what is the size of
each multiplexer?
B. How many selection inputs are needed for MUX A and MUX B?
C. How many inputs and outputs are there in the decoder?
D.How many inputs and outputs are there in the ALU for data ,including
input and output carries?
E.Formulate a control word for the system assuming that the ALU has 35
operations.
Q2: Specify control word
A.R1 R2+R3
B. R4 R4
C. R5 R5-1
D.R6 Shl R1
E. R7 input
Q3:Determine the micro-operations that will be executed in the processor,
when the following 14-bit control words are applied.
a. 00101001100101
b. 00000000000000
c. 01001001001100
d. 00000100000010
e. 11110001110000
Let SP=000000 in the stack. How many items are there in the
stack if
a. Full=1 and Empty=0?
B. . Full=0 and Empty=1?
Convert infix to reverse polish notation
a. A*B+C*D+E*F
b. A*B+A*(B*D+C*E)
c. A+B*[C*D+E*(F+G)]
d. X=A*[B+C*(D+E)]/F*(G+H)
CONVERT arithmetic expressions from reverse polish to infix notation.
A. ABCDE+*-/
B.ABCDE*/-+
C.ABC*/D-EF/+
D.ABCDEFG+*+*+*
