Major blocks in ST Controller
Contd..
● Cortex M0 or M3 processor is based on Von Neumann
Architecture
● Extremely compact and Energy Efficient with small , but essential
Instruction set
● Provides three stage pipelining
● Includes high end processing hardware , including single cycle
multiplier
● Operates on 16 Bit Thumb instruction mode
● Provides high performance with 32 bit Registers
VEENA N HEGDE, 14/7/2022
GIAN COURSE, BMSCE
Block Connection in ST Controller
Mapping of onchip devices with CPU in Cortex M3 - STM
VEENA N HEGDE, 9/8/2022
Clock Connection in ST
● As Shown in previous slide the on chip modules , SDRAM,
Controller Contd…
FLASH and Peripheral Bridge are connected to processor through
a Advanced Highspeed Bus (AHB) to CPU using a multiplexer
● Peripherals are connected to APB1 (Advanced Peripheral Bus1)
and APB2 (Advanced Peripheral Bus2)
● These Peripheral buses are connected to Peripheral Bridge in
which APB to AHB conversion takes place
ARM CORE ARCHITECTURAL
FEATURES
● CORTEX A –PROCESSOR
● CORTEX R – Real Time Processor
● CORTEX M – Generic Embedded Controller
● Cortex M- Low Cost , Low Power , M0, M0+, M3, M4
● Verticals of Embedded System – Consumer Electronics,
Automotive Electronics, Medical Electronics
● I/O Control, Processing and Communication Peripherals
● Examples Washing Machine , Alexa based Home
Automation
● One single system performing one task, Modern Car
ARM CORE ARCHITECTURAL
● M0 FEATURES
- Low Cost
● M0+ - Lower Power
● M3 - Performance Efficiency
● M4 - DSP Control & Accelerated Applications
● Cortex M3 Controller:
● The Controller is supported by ARM Architecture -32 bit
● There will be 32 bit registers r0-r12 , r13 ,r14 and r15 are the Link
register , Program counter and Stack pointer respectively
● The controller has its own inbuilt program flash and data flash
INSTRUCTION SET ARCHITECTURE (ISA)
● The ARM Cortex Controller has instructions which are uniform in
nature provide RISCE features
● Every Instruction is executed in a single cycle
● The instruction execution is supported by 3-stage pipelining
● Instruction Fetch , Decode and Execute stages. The are overlapping,
where one instruction will be in execute , next will be in decode
while the last one will be getting decoded.
● This enhances the speed of operation
● The instructions in ARM instruction mode will be 32 bit
● All registers are 32 bit in nature
Typical Block diagram of a Cortex –M3
controller
INSTRUCTION SET
●TheARCHITECTURE
Cortex M3 controller is (ISA)
supported by Load /Store
Architecture
●The registers r0-r12 are used to store the data or address
●The instructions are register supported
●The RCC provides the clock for operation of the CORE
and peripherals in the controller
●The peripherals operate with respect to clock
●The controller as supported by ARM architecture
CLOCK CONFIGURATION IN STM CONTROLLER
RCC – Reset and Clock Control for Oscillator
● In the Settings
world of embedded processors, power consumption is critical
● The STM32 has a complex clock distribution network which ensures that only those peripherals that
are actually needed are powered.
● This system, called Reset and Clock Control (RCC)
● The RCC module can be used to control the main system clocks and PLLs, any required
configuration
● The STM32 peripherals are organized into three distinct groups called Advanced Peripheral Bus 1
(APB1), Advanced Peripheral Bus 2 (APB2), and Advanced High Speed Bus (AHB)
● APB1 peripherals include the I2C devices, USARTs 2-5, and SPI devices
● APB2 devices include the GPIO ports, ADC controllers and USART 1
● AHB devices are primarily memory oriented including the DMA controllers and external memory
interfaces
○ RCC_APB1PeriphClockCmd(uint32_t RCC_APB1PERIPH , Functional State NewState
○ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB ,
ENABLE);
CORTEX- M3 Controller
Memory
● Usually each of the on Map
programmed
chip peripherals have registers which need to be
○ Input Data Register, Output Data Register , Status Register etc.
● There are two ways to exchange the data between CPU and Peripherals, Port
Mapped I/O and Memory Mapped I/O
● Port mapped I/O requires special instructions , where as memory mapped I/O
treats each peripheral register as if it is a memory location and assigns the
address
● Hence memory space available has to be allocated to peripherals as well apart
from other memory requirements
● The next slide indicates
■ The memory map of CORTEX M3 STM controllers
GPIO IN ARM STM
CONTROLLER ● GPIO – General Purpose
Input/Output
● GPIOA ,GPIO B…16 Bit ports
● Each Pin can be configured
independently
● Each pin is multi functional
● GPIO is also used for Other
peripheral operations such as
USART,SPI, I2C, TIMERS etc
● GPIO Pins cater as input
Analog channels for onchip
ADC operation
Memory Map of STM
● STM supports Register File Architecture
● Memory map for GPIO IS SHOWN
● Half a Giga Byte for ROM (Code
Memory)
● Half a Giga Byte for RAM (Data Memory)
● Half a Giga Byte for GPIO, ADC etc
● External Device such as SD card
● Next is off chip external mem
● System required specific memory
Example of address of a Register of a
Peripheral (GPIO)
Operation of GPIO Peripheral
Clock Enable Operation: Every Peripheral Operates with a Clock;
Corresponding clock has to be enabled
● Clock Enable is needed for 16 pins of any port, hence upper 16 bits are not
used.
RCC AND AHB CLOCK
ENABLING
● #define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002U)
● RCC_AHB2ENR|=RCC_AHB2ENR_GPIOEN;
●
GPIO Mode Register
00- Input Mode
01- Output Mode
10- Alternate Function Mode
11- Analog Mode
Mode Register
15 3 2 1 0
Pin 8 Pin 1
● GPIOB -> MODER |= ~(3UL<<2);
● GPIOB -> MODER |=1
31 18 19 17 16
Basic Structure of Peripheral (GPIO)
GPIO – INPUT OPERATION
INPUT DATA REGISTER IDR
INPUT PUPD REGISTER
OUTPUT TYPE AND SPEED
● The Push Pull state or Open Drain State; High Speed, Medium Speed and Low
REGSITERS
Speed
Program to read an input pin
(Switch)
I/O Pins
● STM32 can be configured as input or output and may be connected to either the GPIO ports or
“alternative functions” (other peripherals)
● GPIO Pins can also be utilized to have analog inputs acting as Analog Channels IN0, IN1… etc. so as
to enable ADC operation
● The initialization of the GPIO modes and pins is generally configured as follows in a pepripheral
library based IDE
○ GPIO_StructInit(&GPIO_InitStructure);
○ fill in structure ...
○ GPIO_Init(GPIOx , &GPIO_InitStructure);
I/O Operation in STM
● Given
● Port A 5th Bit has to be configured as input Pin- A switch is connected
● Port C 13th Bit has been configured as Output Pin –LED Connected
●
○ If the switch is closed , the LED has to glow.
● Solution
○ HSE = 8MHz when Passed through PLL becomes 48 MHz which is
system clock
○ The GPIO Configuration is available in GPIO Driver file
○ Open GPIO Header file available in GPIO.C Driver file
○ The structure GPIO is provided in Header File
○ The function for GPIO Mode, Type , speed identification is written in
the GPIO.C Driver file
○ Using the structure in the GPIO.h file the parameters are defined in
Configuration file , created for GPIO
○ RCC has to be enabled for Both Port A as well as Port C
○ The AHB Clock Enable has to be set both for Port A as well as Port C
○ Since the Input Output initialization operation () function has to be called in
configuration file for Input and Output operations separately,
●
○ Main.h file has to be included
○ stm32_f0xx.h has to be included
○ System_stm32f0xx.h has to be included
○ The Clock configuration has to be included
○ The Systic_clock function has to be called
○ GPIO Configuration function has to be called
Configuration .c file
//Pin 5 of Port A has been configured as input
#include”config.h”
void GPIO_Config(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* GPIOA Periph clock enable */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOC, ENABLE);
// RCC->AHBENR |= ((1<<17) | (1<<19));
•
/* Configure GPIOA Pin5 as Input */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
GPIO_InitStructure.GPIO_Mode = 0x00;
GPIO_InitStructure.GPIO_Speed = 0x03;
GPIO_InitStructure.GPIO_PuPd = 0x00;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Configure the GPIOC Pin13 as Output */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
GPIO_InitStructure.GPIO_Mode = 0x01;
GPIO_InitStructure.GPIO_OType = 0x00;
GPIO_InitStructure.GPIO_Speed = 0x03;
GPIO_InitStructure.GPIO_PuPd = 0x00;
GPIO_Init(GPIOC, &GPIO_InitStructure);
}
main .c file
#include "main.h"
#include "Config.h"
#include "stm32f0xx_it.h"
#include <stdio.h>
uint8_t DataRead = 0;
int main(void)
{
*/ /*Configure systick for Every 1 milli Second*/ SysTick_Config(SystemCoreClock /1000);
/* Call the GPIO Configuration function */
GPIO_Config();
/* Infinite loop */
while (1)
{
DataRead = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_5);
if(DataRead == 1)
{
GPIO_WriteBit(GPIOC, GPIO_Pin_13, 0x01);
}
else
{
GPIO_WriteBit(GPIOC, GPIO_Pin_13, 0x00);
}
REGISTER LEVEL CODE FOR }
GPIO
#include "stm32f0xx.h"
#include "Config.h"
int main(void)
{
/* Initialising syetm clocks */
SysClockConfiguration();
/* GPIO Configuration */
GPIOConfig();
/* Configure TIM6 for Delay function */
DelayTimerConfig();
/* Infinite loop */
while (1)
{
/* SET Pin 8 */
GPIOC->BSRR |= (1U<<8U);
/* Delay of 1 second */
Delay_ms(1000);
/* RESET Pin 8 */
GPIOC->BSRR |= (1U<<24U);
/* Delay of 1 second */
Delay_ms(1000);
/* SET Pin 9 */
GPIOC->BSRR |= (1U<<9U);
/* Delay of 1 second */
Delay_ms(1000);
/* SET Pin 9 */
GPIOC->BSRR |= (1U<<25U);
/* Delay of 1 second */
Delay_ms(1000);
}
