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CAN & FPGA Integration 2.0

The document provides a comprehensive guide on the Controller Area Network (CAN) protocol and its integration with FPGA technology. It outlines the CAN frame format, arbitration process, identifier types, and bit timing, along with the implementation of a CAN logger using FPGA. The guide emphasizes the reliability and efficiency of CAN in various applications, highlighting the advantages of using FPGA for custom system designs.

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Rishabh Raijade
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15 views8 pages

CAN & FPGA Integration 2.0

The document provides a comprehensive guide on the Controller Area Network (CAN) protocol and its integration with FPGA technology. It outlines the CAN frame format, arbitration process, identifier types, and bit timing, along with the implementation of a CAN logger using FPGA. The guide emphasizes the reliability and efficiency of CAN in various applications, highlighting the advantages of using FPGA for custom system designs.

Uploaded by

Rishabh Raijade
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

CAN Protocol and FPGA

Integration
A Comprehensive Guide
By
Rishabhrao Raijade
Introduction to CAN Protocol
Controller Area Network (CAN) is a robust vehicle bus standard. - Allows
microcontrollers and devices to communicate without a host computer. - Commonly
used in automotive, aerospace, and industrial automation. - Supports real-time data
transfer, error detection, and high noise immunity.
CAN Frame Format
Start of Frame (1 bit): Signals start of message - Arbitration Field: - Identifier
(11/29 bits) - RTR bit (Remote Transmission Request) - Control Field (6 bits): Data
length code - Data Field (0-8 bytes): Actual data - CRC Field (15 bits + 1 bit
delimiter): Error detection - ACK Field (2 bits): Acknowledgment - End of Frame
(7 bits): Signals end of message
Arbitration in CAN
Used when multiple nodes attempt to transmit simultaneously.
Non-destructive bitwise arbitration: - Nodes transmit bits and monitor the bus - If a
dominant bit is detected after sending a recessive bit, the node stops transmitting.
Lower ID has higher priority - Ensures fair access and real-time response
CAN Identifiers (IDs)
Standard Frame Format: 11-bit identifier (CAN 2.0A)
Extended Frame Format: 29-bit identifier (CAN 2.0B)
Standard IDs used for critical and frequent messages
Extended IDs allow more nodes and specific categorization - Important for message
prioritization and filtering
Bit Timing in CAN
Ensures synchronization and error-free data transmission
Bit time is divided into: - Synchronization Segment (SYNC)
Propagation Segment (PROP_SEG)
Phase Segment 1 (PHASE_SEG1)
Phase Segment 2 (PHASE_SEG2)
Baud Rate = 1 / (Total Bit Time) - Accurate timing allows multiple devices to remain
synchronized
FPGA Implementation of CAN Logger
Block Diagram: - FPGA Core - CAN Transceiver (e.g., MCP2551) - CAN Controller
(Soft/Hard IP or SPI-based) - UART/USB for logging data - FPGA captures and
stores CAN messages - Enables real-time debugging and data analysis
Applications and Conclusion
Applications: - Automotive ECUs, Industrial Machines, Robotics - Medical
Equipment, Building Automation
Conclusion: - CAN is reliable, real-time, and efficient - FPGA adds flexibility, speed,
and parallel processing - Ideal for custom CAN-based system designs

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