Intel 8085 Microprocessor

Architecture

Dr. Vibhu Jately

Associate Professor
School of Computer Science
Introduction of 8085
Microprocessor is CPU on a Chip.
Introduced in 1976 and is a 8 bit processor.
Intel 8085 is an NMOS microprocessor.
It is a 40 pin IC package fabricated on a single LSI chip.
It uses +5 V for its operation.
Its clock speed is about 3 MHz and clock cycle is 320 ns.
It has 80 basic instructions and 246 opcodes.
Intel has produced large number of peripheral devices for
microprocessor-based system.
Figure 1. Intel 8085 40 pin chip
Figure 2. Block Diagram of Intel 8085
The block diagram shows three important sections:
a) Arithmetic and Logic unit
b) Timing and control unit
c) Set of registers
Arithmetic and Logic Unit
• It performs various arithmetic and logical operations
which includes:
Addition Logical AND
Subtraction Logical OR

Increment Complement

Decrement EX-OR
Timing and Control Unit
• It acts as a brain of the computer system.
• It generate timing, control and status signals which are
required for the operations of processor, memory and I/O
devices.
• It controls data flow between processor, memory and
peripheral devices.

X1
Timing and Control Unit
X2

Crystal oscillator
Registers
Registers are used by the microprocessor for temporary storage
and manipulation of data and instructions.
Data remains in the registers till they are sent to the memory or
I/O devices.
Intel 8085 has following set of registers
a) Accumulator, i.e. register A
b) General purpose register, i.e. B, C, D, E, H, L
c) Stack Pointer
d) Program Counter
e) Instruction register
f) Temporary register
g) Status Flags
 Accumulator
• It is an 8 bit register associated with the ALU.
• It holds one of the operands of the arithmetic and logical
(AL) operation.
• The other operand is stored in the memory or in the
general purpose registers.
• The final result of AL operation is placed in the
accumulator.
• These are true for general cases, not for some typical or
special cases.
Case-I
Some logical instructions need only one operand.
Example-
INR – The content of the accumulator are
incremented by one.
RAL – The content of the accumulator are rotated
left by one bit.
• Some instruction has operand which is of 16 bit.
Example-
DAD – 16 bit addition
One of the operand is in H-L pair and the other is in B-C
or D-E pair. Result is placed in H-L pair.
General Purpose registers
• The 8085 microprocessor has six 8-bit GPR, i.e. B, C, D,
E, H, L.
• To hold 16 bit data a combination of two 8-bit registers can
be employed.
• The combination of two 8 bit register is known as register
pair.
• There are three register pairs, i. e. B-C, D-E, H-L.
• H-L pair is the default memory or data pointer.
 The general purpose registers and accumulator are
accessible to the programmers.
Special purpose registers
a) Program counter –
• It is a 16 bit register which contains or hold the address
of next instruction to be executed.
• It takes care of the program flow or control.
b) Instruction register –
• It is a 8 bit register
• It holds the opcode of the instruction which is being
decoded and executed.
Opcode and Operand
• Instruction contains two parts: operation code (opcode)
and operand.
• Opcode – It specifies the task to be performed by the
computer.
• Operand – It specifies the data to be operated on. It can
be in various forms, i.e.
i. 8 bit or 16 bit data
ii. 8 bit or 16 bit address
iii. Register
 Instruction decoder and Machine cycle Encoder
• After the instruction is fetched in the IR, it is decoded
into this block with the help of Micro program.
• Micro program is a program written by chip designer
(manufacturer) to make the processor understand what a
instruction is or it indicates the type of operation to be
performed for an instruction.
• Number of Machine cycles are assigned according to
the type of instruction.
c) Temporary register
• It is a 8 bit register associated with the ALU.
• It holds the data during an arithmetic and logical
operation.
• It is used by the microprocessor in some instructions.
• They are not accessible by the users.
• W, Z are 8 bit temporary registers.
d) Stack pointer
• It is a 16 bit register which contains the address of the
data present at top of the stack.
• It points to top of stack.
Stack
• It is a part of R/W memory.
• Stores the content of accumulator, flags, program counter,
GPR during the execution of the program.
• Stores the content of Program counter when subroutines
are used.
• Any portion of the memory can be used as stack.
• It is based on LIFO (last in first out).
 Flag register
• The 8085 microprocessor contains five flip-flops to serve as status flags.
• The FF are set/reset according to the condition which arises during an AL
operation.
D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY

• The five flags of 8085 microprocessor are:

a. Carry flag – 1; if there is a carry produced after the execution of an
arithmetic instruction (D7 bit).
0; otherwise
Example: MVI A, 30H (load 30H in register A) MVI B, 40H (load 40H in
register B) SUB B (A = A – B) These set of instructions will set the
carry flag to 1 as 30 – 40 generates a carry/borrow. MVI A, 40H (load
40H in register A) MVI B, 30H (load 30H in register B) SUB B (A = A
– B) These set of instructions will reset the carry flag to 0 as 40 – 30
does not generate any carry/borrow.
• Parity flag – 1; if the no. of binary one is even in A.
0; if the no. of binary one is odd in A.
Example: MVI A 05 (load 05H in register A) This instruction will set the parity flag to
1 as the BCD code of 05H is 00000101, which contains an even number of ones i.e.,
2.
• Auxiliary carry – 1; if there is a carry from D 3 bit to D4 bit.
0; otherwise
Example: MVI A, 2BH (load 2BH in register A) MVI B, 39H (load 39H in register B)
ADD B (A = A + B)
• Zero flag – 1; if the result of AL operation is zero.
0; otherwise
Example: MVI A, 10H (load 10H in register A) SUB A (A = A – A) These set of
instructions will set the zero flag to 1 as 10H – 10H is 00H
• Sign flag- 1; if the result of AL operation is negative.
0; otherwise
Sign flag is judged according to the D7 bit of accumulator.
Example: MVI A, 30H (load 30H in register A) MVI B, 40H (load 40H in register B)
SUB B (A = A – B) These set of instructions will set the sign flag to 1 as 30 – 40 is
a negative number. MVI A, 40H (load 40H in register A) MVI B, 30H (load 30H in
register B) SUB B (A = A – B) These set of instructions will reset the sign flag to 0
as 40 – 30 is a positive number.
Program status word (PSW)

• PSW is a 16-bit register that stores the current status of the

processor. It combines the contents of the 8-bit flag
register and the contents of an 8-bit Accumulator register.
• The PSW contains information about the last operation,
the state of interrupts, and the state of the processor flags.
Figure 3. Intel 8085 Pin Configuration
INTERFACE SECTION
Number of pins in the interfacing section of the
microprocessor depends on the technology of that date.
Cost of an IC depends on the number of pins and the
technology of that date.
8085 microprocessor developed in 1976 has 40 pins.
In today’s scenario technology support 256 pins or more
for interfacing with external world, i.e. memory and I/O
devices.
Through pins different control signals are being
communicated.
Memory and I/O control lines
It is a signal sent by the microprocessor to the
memory/input device to control the read operation. When
it goes low selected memory or input device is read.
= It is a signal sent by the microprocessor to the memory/
output device to control write operation. When it goes low
Data is written into selected
memory or sent to output device.
Ready = It is a signal sent by the input/output device to
the microprocessor to indicate that the input/output device
is ready to send or receive data.
ALE = It is a address latch enable signal.
ALE=1 All 16 lines are used as address bus

ALE=0 A15-A8 = Address bus

AD7-AD0=Data bus
A8-A15 = These are address bus and are used for the most
significant bits of the memory address or I/O address.
AD0-AD7 = These are time multiplexed address/data bus,
i.e.
First clock cycle of a Least significant bits of
machine cycle memory or I/O address
Second and Third clock Used for data transfer
cycle
A machine cycle is the time it takes for a microprocessor
to access memory or I/O devices.
=It is a status signal which distinguishes whether the address
is for memory or I/O.
Status lines (S0 and S1) = These are the signals sent by the
microprocessor to distinguish various types of operations.
S1 S0 Operation
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH

CPU and BUS Control lines

HOLD = When another device of the computer system,
requires address/data bus for data transfer, it sends HOLD
signal to the microprocessor.
 HLDA = It is a HOLD acknowledge signal sent out by the microprocessor
after receiving the HOLD signal.

Memory

Microproces
DMA
sor
Controller

I/O device

 DMA (Direct Memory Access) controller is an external device that controls

the transfer of data between memory and input/output (I/O) devices.
 RESET IN = It reset the program counter, interrupt enable, HLDA flip-
flops and instruction register.
 RESET OUT = It indicates that the CPU is being reset.
Interrupt
• Interrupt is an internal or external signal which may disturb or alter
the sequence of execution of processor.
• It is a method by which an I/O device informs the processor that it
requires services of the processor.
Interrupt can be classified as:
a. Maskable – Interrupt which can be avoided.
Non-Maskable - Interrupt which cannot be ignored or
avoided.
b. Vectored – Interrupt which has specific address location in the
memory.
Non-vectored – Interrupt which do not have specific address
location in the memory.
Vectored and Non-Vectored Interrupts
In a vectored interrupt, each device is assigned a unique code,
typically four to eight bits in length. When a device interrupts,
it sends its unique code over the data bus to the processor. The
processor uses the code to determine which interrupt service
routine to execute.
In a non-vectored interrupt, the peripheral provides the address
of the interrupt service routine directly to the processor. This
requires more time for an interrupt to be serviced because the
address must be retrieved from the interrupting device every
time the interrupt is triggered.
Priority Interrupt Type of Triggering Vector Address

1 TRAP V 0024 H
E
2 M RST 7.5 C 003C H
A T
S O
3 RST 6.5 R 0034 H
K
A E
4 B RST 5.5 D 002C H
L
5 E INTR

Level Triggering Edge

Triggering
TRAP: The TRAP interrupt is a non-maskable interrupt that is
generated by an external device, such as a power failure or a hardware
malfunction. The TRAP interrupt has the highest priority and cannot
be disabled.
RST 7.5: The RST 7.5 interrupt is a maskable interrupt that is
generated by a software instruction. It has the second highest priority.
RST 6.5: The RST 6.5 interrupt is a maskable interrupt that is
generated by a software instruction. It has the third highest priority.
RST 5.5: The RST 5.5 interrupt is a maskable interrupt that is
generated by a software instruction. It has the fourth highest priority.
INTR: The INTR interrupt is a maskable interrupt that is generated by
an external device, such as a keyboard or a mouse. It has the lowest
priority and can be disabled.
Crystal and serial I/O lines
X1 and X2 = These are the terminals connected to external
crystal oscillator which drives an internal
circuitry of the microprocessor.
SID = It is a data line for serial input. The data on this line is
loaded into the 7th bit of the accumulator when Read Interrupt
Mask (RIM) is executed.
 RIM instruction reads the current value of the Interrupt Mask
Register (IMR) and copies it to the accumulator.
 An interrupt mask register (IMR) is a read and write register that
specifies which interrupts should be ignored.
SOD = It is a data line for serial output. The 7 th bit of the
accumulator is output on SOD line when Set
Interrupt Mask (SIM) instruction is executed.
 SIM instruction allows the microprocessor to selectively enable or
disable interrupts by setting the appropriate bits in the IMR.
Utility lines
Vcc = +5 V supply
Vss = ground reference
Clock = It is a output for user, which can be used for other
digital ICs.
INSTRUCTION
An instruction is a command given to the microprocessor
to perform a given task on specified data.
Instruction have two parts:
Opcode (Operation code)- It specifies the task to be
performed.
Operand – It specifies the data to be operated on and is
defined in various forms such as:
a. 8 bit or 16 bit data
b. 8 bit or 16 bit address
c. Internal register or a memory location
Instruction Word Size
Instructions in 8085 microprocessor are classified into the
following three groups according to the word (byte) size:
a. One byte instruction
b. Two byte instruction
c. Three byte instruction
One byte instruction
A one byte instruction includes the opcode and operand in
the same byte.
Task Opcode Operand Binary code Hex code

Copy the contents MOV C, A 0100 1111 4FH

of the accumulator
in register C

Add the contents ADD B 10000000 80H

of register B to the
contents of the
accumulator
Invert each bit in CMA 0010 1111 2FH
the accumulator
Two Byte instruction
In a two byte instruction, the first byte specifies the
operation code and the second byte specifies the operand.

Task Opcode Operand Binary code Hex Code

Load an 8 MVI A,32H 0011 1110 3E

bit data in 00110010 32
the
accumulator
Load an 8 MVI B,F2H 00000110 06
bit data in 11110010 F2
register B
Three byte instruction
In a 3 byte instruction, the first byte represent the opcode
and the second and the third byte represents the operand
(16 bit address).
Task Opcode Operand Binary code Hex Code

Load the contents LDA 2050H 0011 1010 3A

of the memory 0101 0000 50
2050H into A 0010 0000 20

Transfer the JMP 2085H 1100 0011 C3

program 1000 0101 85
sequence to 0010 0000 20
memory location
2085H
 Microprocessor Communication and Bus timings
• A program constitutes a set of Instructions. The processor
fetches one instruction from the memory at a time and
executes it.
• The necessary steps that a processor carries out to fetch an
instruction and data from memory and I/O devices,
constitutes an instruction cycle.
Fetch cycle Processor fetches opcode from memory

Execute cycle Processor gets data from memory or I/O

devices and perform specific operation

Instruction Fetch cycle+ Execution cycle

cycle
Fetch operation
The microprocessor places the 16 bit memory address
from the program counter to the memory address register
(MAR). The contents of MAR is transferred to the
memory through the address bus.
 The control unit sends the control signal , to the memory.
 The opcode from the memory location is placed on data
bus.
The opcode first come in the memory data register
(MDR) and from there it goes to Instruction register.
The instruction is decoded in the instruction decoder.
Data Flow from memory to the Microprocessor
 Memory
Instruction MDR Data Bus
Register
Memory
Instruction Address
Program Bus
Decoder MAR
Counter
Control

Flow of Instruction code

Send address Memory gets opcode Transfer opcode to

to memory from memory location processor
Clock

Time
A Typical Fetch Cycle
Execute Operation
After the instruction is being decoded, execution begins.
If the operand is in the GPR (one byte instruction), then
execution is immediately performed and the time taken is
one clock cycle.
If the instruction contains data or memory address (two or
three byte instruction).
Processor performs read operation and gets data from the
memory.
In some instruction write operation is performed.
Execution cycle contains one or more read cycles.
 Instruction cycle

Fetch cycle Execute cycle

Cloc
k

Instruction cycle showing FC, EC, IC

a. Instruction cycle – Time required to complete the execution of
an instruction.
b. Machine cycle – Time required to complete one operation of
either accessing memory, I/O device.
Example- Fetch, Read, Write.
c. T-state- One sub division of the operation performed
in one clock cycle. T-state and clock period
are often used synonymously.
Demultiplexing the Bus
• The address/data bus transmits data and address at
different moments.
• Address /data bus are time multiplexed.
• The demultiplexing is done through latch and the ALE
signal.
• When ALE is high Output changes according
to the input signal.
• When ALE is low The bus is used for carrying
the data.
74LS373 is
a 8-bit latch
for bi-
directional
data
transfer.

Schematic of Latching Low-Order Address Bus

Generating Control Signals
There are different control signals which are required for
the operation of microprocessor.
The , , are different control signals.
These signals are combined to generate four different
signals, i.e.
8085 Control Signals

Operation Control
Signals

0 0 1 Fetch

0 0 1 M/M Read

0 1 0 M/M Write

1 0 1 I/O Read

1 1 0 I/O Write
 74LS32
8085

𝐼𝑂/ 𝑀 𝑀𝐸𝑀𝑅
𝑅𝐷
𝑊𝑅
𝑀𝐸𝑀𝑊
74LS04

𝐼𝑂𝑅

𝐼𝑂𝑊

Schematic to Generate Read/Write Control Signals for Memory and IO

 A15 A15
A8 A8 Address
ALE
E A7 Bus
AD7 A0
N
Latch
74LS32
AD0
D0
Data Bus
D7
𝐼𝑂/ 𝑀 𝑀𝐸𝑀𝑅
𝑅𝐷
𝑊𝑅
𝑀𝐸𝑀𝑊
74LS04

𝐼𝑂𝑅

𝐼𝑂𝑊
8085 Demultiplexed Address and Data Bus with Control Signals
 Instruction Set and
Programming of Intel
8085 Microprocessor
Dr. Vibhu Jately
Associate Professor
School of Computer Science
Instruction Set
An instruction is a command given to the computer to
perform a specified operation on a given data.
The instruction set is the collection of instructions which
the microprocessor is designed to execute.
The assembly language program comprises of the
collection of instructions to perform a certain operation.
Different companies such as Intel, Motorola, etc. have
different instruction set.
 Instruction

Type of operation Length of Instruction

Data transfer/ Copy 1 Byte Instruction
Instruction
Arithmetic Instruction 2 Byte Instruction
Logical Instruction
3 Byte Instruction
Branching Instruction

Machine control
Instruction
 Data Transfer Instruction
• These instructions are used to transfer data from one
location to another, i.e. source to destination. It may
include:
 Register Register (MOV A, B)
 Register Memory (MOV M, r and MOV r, M )
 Data Register (MVI r, data)
Arithmetic Instruction
• These instructions are used to perform arithmetic
operations like addition, subtraction, increment,
decrement. Example- ADD, SUB, INR, DCR, etc.
 Logical Instruction
• These instructions perform logical operations such as
AND, OR, compare, rotate, X-OR. Example- ANA, ORA,
CMP, RAL, XRA.
Branching Instruction
• The instruction under this group performs conditional and
unconditional jump, subroutine call and return and restart.
Example- JMP, CALL, RST, etc.
I/O and Machine control Instruction
• This group of instruction includes instruction for
input/output ports, stack and machine control operations.
Example- IN, OUT, PUSH, POP, HLT, etc.
DATA FORMAT
• There are various techniques of specifying data for an
instruction. These can be defined as:
 Instruction itself includes 8 bit/16 bit data
 Instruction includes address of the memory location, I/O
port.
 Instruction has only one register.
 Instruction has two register.
 In some instruction data is implied.
ADDRESSING MODES
• Instruction has opcode and operand. There are different
techniques to specify operand in an instruction. These
techniques are called as addressing modes.
• Intel 8085 has the following addressing modes:
a) Direct addressing mode
b) Register addressing mode
c) Register indirect addressing mode
d) Immediate addressing mode
e) Implicit/Implied addressing mode
a) Direct addressing mode
• Address of the operand (data) is given in the instruction
itself.
• Example-

LDA 6000H Load the accumulator with the contents of the

memory location 6000H
STA 2400H Store the contents of the accumulator in the
memory location 2400H
IN 02 The data available on the 8 bit address of the
input port is moved to the accumulator
b) Register addressing mode
• Operand is in one of the GPR or the accumulator.
• Opcode specifies the operation to be performed and
address of the registers.
• Operation takes place between registers.
• Example-
MOV A, B Move the content of the register B to register A

ADD B Add the content of the register B to the content of

the register A
c) Register Indirect addressing mode
• Address of the data is present as the content of the another register
pair. (Address of the operand is specified by a register pair)
• Example

LXI H, 2500H Load H-L pair with 2500 H

MOV A,M Move the content of the memory location whose address is
in H-L pair to the accumulator
HLT Halt

LXI H, 2500H Load H-L pair with 2500 H

ADD M Add the content of the memory location whose address is in

H-L pair to the content of the accumulator
HLT Halt
d) Immediate addressing mode
• In this addressing mode the operand (data) is specified
within the instruction itself.
• Example
MVI A,05 Move the data 05 into the accumulator

ADI 06 Add 06 to the content of the accumulator

LXI H, 2500 2500 is 16 bit data and is loaded into H-L pair
e) Implicit/ Implied addressing mode
• In this type of instruction, operand is the content of the
accumulator.
• No data, address of data, register are present in the
instruction.
• Example
CMA Complement the content of the accumulator

RAL Rotate accumulator left through carry

RAR Rotate accumulator right through carry

RLC Rotate accumulator left

Symbols and Abbreviations
addr 16-bit address of the memory location
data 8-bit data
data 16 16-bit data
r,r1,r2 One of the register A, B, C, D, E, H, L
A, B, C, D, H, L 8-bit register
A Accumulator
M Memory whose address is in H-L pair
H Appearing at the end of a group of digits specifies
hexadecimal
rp Represents one of the register pair
B represents B-C pair
D represents D-E pair
H represents H-L pair
[] The content of the register identified within the brackets

[[]] The content of the memory location whose address is in the

register pair identified within the brackets
 Data Transfer Group
Instruction Operation Machine States Addressing
cycles Mode
MOV A, B Move the content of register B to 1 4 Register
register A Addressing
MOV r, M Move the content of memory to 2 7 Register
register. Indirect
MOV M, r Move the content of the register to the 2 7 Register
memory location addressed by H-L pair. Indirect

MVI r, data Move immediate data to the register 2 7 Immediate

MVI M, data Move the immediate data to memory 3 10 Immediate/

location addresses by H-L pair Reg. Indirect

LXI rp, data 16 Load the register pair with the 16 bit 3 10 Immediate
data
LDA addr Load the accumulator with the content 4 13 Direct
of the specified address in the
instruction
STA addr Store the content of the accumulator in the specified 4 13 Direct
memory location
LHLD Load the content of the specified memory location in 5 16 Direct
addr the address to the L register and the content of the next
memory location is loaded into H.

SHLD Store the content of the L register in the specified 5 16 Direct

addr address in the instruction and the content of the H
register is stored in the next memory location.

LDAX rp Load the accumulator with the content of the address 2 7 Register
stored in the rp Indirect

STAX rp Store the content of the accumulator in the memory 2 7 Register

location whose address is in the register pair rp. Indirect

XCHG Exchange the contents of H-L pair with D-E pair. 1 4 Register
Arithmetic Group
Instruction Operation Machine States Addressing
Cycles Modes
ADD r Add register to accumulator. [A] [A]+[r] 1 4 Register

ADD M Add the content of the memory to accumulator 2 7 Register

[A] [A]+[[H-L]] Indirect

ADC r The content of register r and carry status are added 1 4 Register
with the content of the accumulator
ADC M The content of the memory location addressed by 2 7 Register
H-L pair and carry status are added to the content of Indirect
the accumulator. Sum in the accumulator.
ADI data Add immediate data to accumulator 2 7 Immediate
[A] [A]+data
ACI Data The 2nd byte of the instruction (which is data) and 2 7 Immediate
the carry status is added to the content of the
accumulator
DAD rp Add the content of register pair rp to the content of 3 10 Register
H-L pair [H-L] [H-L]+[rp]
SUB r Subtract register from memory [A] [A]-[r] 1 4 Register
Instruction Operation Machine States Addressing
Cycles Modes
SUB M Subtract data in memory (H-L pair) from 2 7 Register
accumulator [A] [A]-[[H-L]] Indirect
SBB r The content of register r and carry status are 1 4 Register
subtracted from the content of the accumulator.
SBB M The content of the memory location addressed by 2 7 Register
H-L pair and carry status are subtracted from the Indirect
content of the accumulator.
SUI data Subtract immediate data from accumulator 2 7 Immediate
[A] [A]-data

SBI data The data and carry status are subtracted from the 2 7 Immediate
content of the accumulator

INR r Content of register r are incremented by one 1 4 Register

[r] [r]+1

INR M Increment the content of memory location in H-L 3 10 Register

pair by one Indirect
[[H-L]] [[H-L]]+1
DCR r Decrement the content of register by one 1 4 Register
[r] [r]-1

DCR M Decrement the content of memory location in H-L 3 10 Register

pair by one [[H-L]] [[H-L]]-1 Indirect
Instruction Operation Machine States Addressing
Cycles Modes
INX rp Increment the content of register pair rp by one 1 6 Register
[rp] [rp]+1

DCX rp Decrement the content of register pair rp by one 1 6 Register

[rp] [rp]-1

DAA Converts the content of accumulator from 1 4 NA

Hexadecimal to Decimal
Logical Group
Instruction Operation Machine States Addressing
Cycles Modes
ANA r The content of register r is ANDed with the content of 1 4 Register
accumulator
ANA M The content of the memory location addressed by H-L 2 7 Register
pair is ANDed with content of accumulator Indirect

ANI data The data is ANDed with the content of the accumulator 2 7 Immediate

ORA r The content of the register is ORed with the content of the 1 4 Register
accumulator
ORA M The content of the memory location addressed by H-L 2 7 Register
pair is ORed with content of accumulator Indirect

ORI data The data is ORed with the content of the accumulator 2 7 Immediate

XRA r The content of the register r is EXCLUSIVE-ORed with 1 4 Register

the content of the accumulator
Instruction Operation Machine States Addressing
Cycles Modes

XRA M The content of the memory location addressed by H-L 2 7 Register

pair is EXCLUSIVE-ORed with content of accumulator Indirect

XRI data The data is EXCLUSIVE-ORed with the content of the 2 7 Immediate
accumulator
CMA Complement the content of the accumulator 1 4 Implicit
CMC The CS Flag is complemented 1 4 NA

STC The status Flag CS is set to 1. 1 4 NA

CMP r The content of the register r is subtracted with the content 1 4 Register
of the accumulator and the status flag are set according to
the result. The accumulator remains unchanged.
CMP M The content of the memory location addressed by H-L 2 7 Register
pair is subtracted with the content of the accumulator and Indirect
the status flag are set according to the result. The result of
the accumulator remains unchanged.
CPI data The data is subtracted from the content of the accumulator 2 7 Immediate

RLC The content of the accumulator is rotated left by one bit 1 4 Implicit
without carry
Instruction Operation Machine States Addressing
Cycles Modes

RRC The content of the accumulator is rotated right by one bit 1 4 Implicit
without carry
RAL The content of the accumulator is rotated left by one bit 1 4 Implicit
with carry
RAR The content of the accumulator is rotated right by one bit 1 4 Implicit
with carry
Branch Group
 The instruction in this group change the normal sequence of the
program.

Conditional

Branch Group

Unconditional

 Unconditional- The program is transferred to a specified memory

location unconditionally.
 Conditional- The program is transferred to a specified memory location
when certain condition is satisfied.
 Unconditional instructions
• JMP addr- Program jump to the instruction specified by the address
(label) unconditionally. Machine Cycles – 3, States – 10, Addressing Mode
- Immediate
Conditional instructions: If the condition is true - 3 Machine
Cycles (10 States), if the condition is false 2 machine cycles (7 States)

Instruction Operation Addressing Mode

JZ addr Jump if the result is zero
JNZ addr Jump if the result is non-zero
JC addr Jump if there is a carry
JNC addr Jump if there is no carry Immediate
JP addr Jump if the result is plus
JM addr Jump if the result is minus
JPE addr Jump if even parity
JPO addr Jump if odd parity
Instruction Operation Machine States Addressing
Cycles Mode
CALL addr Unconditional CALL: call the 5 18 Immediate/Reg.
subroutine identified by address Indirect

Conditional Conditional CALL: call the subroutine 2/5 9/18 Immediate/Reg.

CALL addr if the condition is true Indirect
CC addr – Call subroutine if CS = 1
CNC addr – Call subroutine if CS = 0
CZ addr – Call subroutine if Z = 1
CNZ addr – Call subroutine if Z = 0
CP addr – Call subroutine if S = 0
CM addr – Call subroutine if S = 1
CPE addr – Call subroutine if P = 1
CPO addr – Call subroutine if P = 0
RET. Return from subroutine. Used at the end 3 10 Register
of subroutine Indirect
Instruction Operation Machine States Addressing
Cycles Mode
Conditional If the condition is true, the program 1/3 6/12 Reg. Indirect
Return return from the subroutine
RC–Return from subroutine if CS = 1
RNC–Return from subroutine if CS = 0
RZ–Return from subroutine if Z = 1
RNZ–Return from subroutine if Z = 0
RP–Return from subroutine if S = 0
RM–Return from subroutine if S = 1
RPE–Return from subroutine if P = 1
RPO–Return from subroutine if P = 0
PCHL Contents of H-L pair transferred to 1 6 Register
program counter
Machine control Group
Instruction Operation Machine
Cycles
IN port-address The data available on the port is moved to the 03
accumulator
OUT port- The content of the accumulator is moved to 03
address the port specified by its address
HLT The program execution is stopped 01
Timing diagram
It is a graphical representation of necessary steps which
are carried out in a machine cycle.
Pictorial representation of execution of an instruction with
the help of various control/timing and status signals.
Based on different sets of operations carried out in 8085
microprocessor, there are different timing diagram:
a. Opcode fetch
b. Memory read
c. Memory write
d. I/O read
e. I/O write
Timing diagram for Opcode Fetch Cycle
Sequence of steps for opcode fetch operation
• First clock cycle (T1)- Microprocessor sends the address
of the memory where the opcode is available.
• Second clock cycle (T2) – The control unit sends the
control signal to the memory chip to enable the read
operation. The byte is placed from the memory location
on the data bus.
• Third clock cycle (T3) – The opcode is placed in the IR.
• Fourth clock cycle (T4)- The opcode is decoded.
Timing diagram for MVI A, Data
Sequence of steps for memory read operation
• First clock cycle (T1)- Microprocessor sends the address
of the memory where the data is available.
• Second clock cycle (T2) – The control unit sends the
control signal to the memory chip to enable the read
operation. The byte is placed from the memory location
on the data bus.
• Third clock cycle (T3) – The data enters the CPU.
Timing diagram for Opcode fetch, Memory &
IO read operation
Timing diagram for memory write Operation
Sequence of steps for memory write operation
• First clock cycle (T1)- Microprocessor sends the address
of the memory where the data is to be stored.
• Second clock cycle (T2) – The control unit sends the
control signal to the memory chip to enable the write
operation.
• Third clock cycle (T3) – The byte is placed from the
microprocessor on the data bus and stored in memory.