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Module 5: Memory
Management
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Overview: 13
Virtual memory systems
Translation Lookaside Buffer (TLB)
Memory system reliability in terms of error correction and
error detection.
Virtual memory systems 14
The primary memory can turn as a “cache” for the hard disk /external
storage. This practice is termed as “virtual memory”.
(Note: Active portions of a software resides in primary memory but cache contains
frequent or active data of a running program. )
Virtual memory serves in two ways. Firstly, it helps one to expand the
usage of physical memory by disk usage. Second , it helps us to preserve memory,
since every virtual address is converted into a physical address.
Most design decisions are influenced by the high cost of a page fault
in virtual memory systems. It will take millions of clock cycles to transfer a page
fault to disk.
Basic Terms 15
Page Frames or Frames:
Main memory is divided into fixed size of small blocks.
Pages:
Logical memory is divided into small and same size of blocks.
Swap Space:
The virtual machine usually creates the space on flash memory or
disk for all the pages of a process when it creates the process. This
space is called the swap space.
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Demand Paging Method 17
In the demand paging method, where processes are stored in secondary
memory, and pages are loaded on demand only, not before.
When a context switch happens, after loading the first page, the
computer system starts running the new program and fetches the pages of that
program as they are referenced.
Advantages:
- Minimum I/O operations.
- Minimum Memory required.
- Quick response.
- Allow more user programs.
Basic Terms (Continued…) 18
Dirty bit:
To track whether a page has been written since it was read into the
memory, a dirty bit is added to the page table. The dirty bit
is set when any word in a page is written. If the operating system
chooses to replace the page, the dirty bit indicates whether the page
needs to be written out before its location in memory can begiven
to another page. Hence, a modified page is often called a dirty page.
Valid bit:
If the valid bit is on, the page table supplies the physical page
number (i.e., the starting address of the page in memory)
corresponding to the virtual page. If the valid bit is off , the
page currently resides only on disk, at a specified disk
address..
Memory Mapping 19
Logical Address Physical Address
Physical Memory
CPU P D F D
F
Page Table
v d P F
Memory Mapping (Continued…) 20
CPU generated logical address, which consist of a page number “p” and
a page offset “d”.
Page table contains page number (is act as an index) and page frame
number.
Physical address is generated by combining page frame number “f” with
page offset “d”.
If logical address is m bits and page size is 2^n words then the logical
address space is 2^m and (m-n) bits are assigned to page number.
Example Problem: 1 21
1) If virtual address is 32 bits and size of page is 4kB then find how
many bits are required to define page number and page offset?
2) If a computer hardware has a page with 4096 bytes and a process
required 73,655 bytes then find the number of frames need to store
the process in memory?
3) If a computer system has a 48-bits logical address, 8 bytes page
table entry and 4 kB pages, then find the size of page table.
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Drawback:
If page table is very large then implementation of fast registers for most modern
computers are not feasible.
With the use of Page Table Base Register (PTBR), we can reduce context switching
time. Since this scheme needs 2 memory accesses, to overcome this issue a speedy
lookup cache called Translation Lookaside Buffer (TLB) was proposed.
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Translation Lookaside Buffer (TLB)
A translation lookaside buffer (TLB) is a cache that stores latest translations of
physical addresses to logical memory for quicker retrieval.
Each row of TLB consists of a tag and a value.
When the associative memory can be obtained with an item, all the tags match the
item at the same time.
When the element is located it returns the corresponding value field. The search is
quick; however, the hardware is expensive..
Memory Mapping along with TLB 24
Logical Address Physical Address
Physical Memory
CPU P D F D
TLB F
v d P F
TLB
Miss
v d P F
Page Table
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Example Problem : 2
1) If the TLB hit ratio is 0.6, 60 msec to access main memory and 30 msec to
search the TLB then find the effective access time ?
2) In a paging system, the translation Look-a-side Buffer (TLB) hit ratio is
50%, it takes 40 ns to search TLB and 120 ns to access the main memory.
Compute effective memory access time?
3) A TLB-access takes 15 ns, hit ratio is 92% and physical memory
access takes 45 ns. What is the effective memory access time?
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Solutions
1) If the TLB hit ratio is 0.6, 60 msec to access main memory and 30 msec to
search the TLB then find the effective access time ?
Ans:
Effective Memory access (EMA)
= 0.6 * (30 +60) ms + 0.4
*(30+ 60+ 60) ms
EMA = 54 ms + 60 ms = 114 ms .
2) In a paging system, the translation Look-a-side Buffer (TLB) hit ratio is
50%, it takes 40 ns to search TLB and 120 ns to access the main memory.
Compute effective memory access time?
Ans:
EMA = .5 *(40 +120) + .5 *(40+120+120) ns = 80 + 140 = 220 ns.
3) A TLB-access takes 15 ns, hit ratio is 92% and physical memory access
takes 45 ns. What is the effective memory access time?
Ans:
EMA = .92 *(15 + 45) + .08 * (15 +45 +45)ns = 55.2 + 8.4 = 63.6ns.
