Data Types in
Verilog
Prepared By
Dr Sidharthan V
Asso Professor & Head,
Department of Electronics,
Sri Ramakrishna College of Arts and Science,
Coimbatore -6
Value Set:
•Verilog consists of only four basic values. Almost all Verilog data types
store all these values:
0 (logic zero, or false condition)
1 (logic one, or true condition)
x (unknown logic value)
x and z have limited use for synthesis.
z (high impedance state)
WIRE:
• A wire represents a physical wire in a circuit and is used to connect gates or modules.
The value of a wire can be read, but not assigned to, in a function or block.
• A wire does not store its value but must be driven by a continuous assignment
statement or by connecting it to the output of a gate or module.
• Other specific types of wires include:
wand (wired-AND);:the value of a wand depend on logical AND of all the drivers
connected to it.
wor (wired-OR);: the value of a wor depend on logical OR of all the drivers connected
to it.
tri (three-state;): all drivers connected to a tri must be z, except one (which
determines the value of the tri).
Syntax:
wire [msb:lsb]
wire_variable_list;
wand [msb:lsb]
wand_variable_list;
wor [msb:lsb]
wor_variable_list;
tri [msb:lsb]
tri_variable_list;
REGISTER:
• A reg (register) is a data object that holds its Syntax
value from one procedural assignment to the
next. reg [msb:lsb]
reg_variable_list;
• They are used only in functions and
procedural blocks.
• A reg is a Verilog variable type and does not
necessarily imply a physical register.
• In multi-bit registers, data is stored as
unsigned numbers and no sign extension is
done for what the user might have thought
were two’s complement numbers.
Input, Output and inout:
Syntax
input [msb:lsb]
• These keywords declare input, input_port_list;
output and bidirectional ports of a output [msb:lsb]
module or task. output_port_list;
inout [msb:lsb]
• Input and inout ports are of type inout_port_list;
wire.
• An output port can be configured
to be of type wire, reg, wand, wor
or tri.
• The default is wire.
Integer:
• Integers are general-purpose Syntax
variables. integer
• For synthesis they are used mainly integer_variable_list;
loops-indicies, parameters, and
constants. ... integer_constant ... ;
• They are of implicitly of type reg.
However they store data as signed
numbers whereas explicitly declared
reg types store them as unsigned.
• If they hold numbers which are not
defined at compile time, their size will
default to 32-bits.
• If they hold constants, the synthesizer
adjusts them to the minimum width
needed at compilation.
Time:
• Time is a 64-bit quantity that Syntax
can be used in conjunction
with the $time system task to time time_variable_list;
hold simulation time.
• Time is not supported for
synthesis and hence is used
only for simulation purposes.
Parameter:
Parameter
A parameter defines a constant that can
be set when you instantiate a module.
This allows customization of a module
during instantiation.
Syntax
parameter par_1 = value,
par_2 = value, .....;
parameter [range]
parm_3 = value
