Module 4
Delay Estimation
RC Delay model
Effective Resistance
The RC delay model treats a transistor as a switch in series with a
resistor.
The effective resistance is the ratio of Vds to Ids averaged across the
switching interval of interest.
Effective Resistance
A unit nMOS transistor is defined to have effective resistance R
An nMOS transistor of k times unit width has resistance R/k because it
delivers k times as much current.
A unit pMOS transistor has greater resistance, generally in the range of
2R–3R, because of its lower mobility. We will use 2R for examples to
keep arithmetic simple.
Gate and Diffusion capacitance
Each transistor also has gate and diffusion capacitance.
We define C to be the gate capacitance of a unit transistor of either
flavor.
A transistor of k times unit width has capacitance kC.
Diffusion capacitance depends on the size of the source/drain region.
Wider transistors have proportionally greater diffusion capacitance.
Increasing channel length increases gate capacitance proportionally but
does not affect diffusion capacitance.
Effective Resistance
Effective Resistance
Equivalent RC circuits
RC circuits- Example 1
Sketch a 3-input NAND gate with transistor widths chosen to achieve
effective rise and fall resistance equal to that of a unit inverter (R).
Annotate the gate with its gate and diffusion capacitances. Assume all
diffusion nodes are contacted. Then sketch equivalent circuits for the
falling output transition and for the worst-case rising output
transition.
RC circuits- Example 1
Each transistor has resistance R/3 and the series
combination has resistance R.
The two pMOS transistors are in parallel. In the
worst case (with one of the inputs low), only one of
the pMOS transistors is ON. Therefore, each must
be twice unit width to have resistance R.
RC circuits- Example 1
Figure shows the capacitances. Each input
presents five units of gate capacitance to
whatever circuit drives that input. Notice that
the capacitors on source diffusions attached
to the rails have both terminals shorted
together so they are irrelevant to circuit
operation.
RC circuits- Example 1
RC circuits- Example 1
Elmore Delay
In general, most circuits of interest can be represented as an RC tree,
i.e., an RC circuit with no loops. The root of the tree is the voltage
source and the leaves are the capacitors at the ends of the branches.
The Elmore delay model estimates the delay from a source switching to
one of the leaf nodes changing as the sum over each node i of the
capacitance Ci on the node, multiplied by the effective resistance Ris on
the shared path from the source to the node and the leaf.
Application of Elmore delay is best illustrated through examples.
Elmore Delay-Example 1
Compute the Elmore delay for Vout in the 2nd order RC system from
given Figure
Elmore Delay-Example 1
The circuit has a source and two nodes.
At node n1, the capacitance is C1 and the resistance to the source is
R1.
At node Vout, the capacitance is C2 and the resistance to the source is
(R1 + R2).
Hence, the Elmore delay is tpd = R1C1 + (R1 + R2)C2
Elmore Delay-Example 2
Estimate tpd for a unit inverter driving m identical unit inverters.
Elmore Delay-Example 2
Figure shows an equivalent circuit for the falling transition.
Each load inverter presents 3C units of gate capacitance, for a total of 3mC.
The output node also sees a capacitance of 3C from the drain diffusions of the
driving inverter.
The parasitic capacitance is independent of the load that the inverter is
driving.
Hence, the total capacitance is (3 + 3m)C. The resistance is R, so the Elmore
delay is tpd = (3 + 3m)RC.
The equivalent circuit for the rising transition gives the same results.
Elmore Delay-Example 3
Repeat previous Example if the driver is w times unit size.
Elmore Delay-Example 3
The Elmore delay is tpd= ((3w+ 3m)C)(R/w)= (3 + 3m/w)RC.
Define the fanout of the gate, h, to be the ratio of the load capacitance
to the input capacitance. (Diffusion capacitance is not counted in the
fanout.) The load capacitance is 3mC. The input capacitance is 3wC.
Thus, the inverter has a fanout of h=m/w and the delay can be written
as (3 + 3h)RC
Elmore Delay-Example 4
If a unit transistor has R= 10 k and C = 0.1 fF in a 65 nm process,
compute the delay, in picoseconds, of the inverter in Figure with a
fanout of h= 4.
Elmore Delay-Example 4
The RC product in the 65 nm process is (10 k )(0.1 fF) = 1 ps
For h= 4, the delay is (3 + 3h)(1 ps) = 15 ps.
This is called the fanout-of-4 (FO4) inverter delay and is representative
of gate delays in a typical circuit. Remember that a picosecond is a
trillionth of a second. The inverter can switch about 66 billion times per
second. This stunning speed partially explains the fantastic capabilities
of integrated circuits.
Elmore Delay-Example 5
Estimate tpdf and tpdr for the 3-input NAND gate from previous
Example if the output is loaded with h identical NAND gates.
Elmore Delay-Example 5
Each NAND gate load presents 5 units of capacitance on a given input.
tpdf = (3C)(R/3)+(3C)(R/3 + R/3)+((9+ 5h)C)(R/3 +R/3 + R/3)=(12+
5h)RC.
tpdr= (15 + 5h)RC
Linear Delay Model
Delay has two components namely effort delay and parasitic
delay
1. Effort delay f= g.h
2. Logical effort (g) measures the relative ability of a gate
to deliver current
3. Electrical effort (h) Ratio of output to input capacitance
4. Parasitic delay (p) - Set by internal parasitic capacitance
when no load is attached.
Delay d=f+p
Linear Delay Model
The complexity is represented by the logical effort, g .
An inverter is defined to have a logical effort of 1.
More complex gates have greater logical efforts, indicating that
they take longer to drive a given fanout.
For example, the logical effort of the 3-input NAND gate from
the previous example is 5/3.
A gate driving h identical copies of itself is said to have a fanout
or electrical effort of h. If the load does not contain identical
copies of the gate, the electrical effort can be computed as
Linear Delay Model
Logical effort
Logical effort of a gate is defined as the ratio of the input
capacitance of the gate to the input capacitance of an inverter
that can deliver the same output current.
Logical effort indicates how much worse a gate is at producing output
current as compared to an inverter, given that each input of the gate
may only present as much input capacitance as the inverter.
Logical effort
Logical effort
Cin NAND gate=5
Cin Inv=3
g=5/3
Logical effort
Cin NOR gate=7
Cin Inv=3
g=7/3
Logical effort
Parasitic Delay
The parasitic delay of a gate is the delay of the gate when it drives zero
load.
Parasitic delay is the ratio of diffusion capacitance to gate capacitance
in a particular process.
Parasitic Delay
