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Nano Programming

Nanoprogramming introduces a two-level control memory system in processors, consisting of microcontrol memory (μCM) for microinstructions and nanocontrol memory (nCM) for nanoinstructions, enhancing efficiency and reducing control memory size. The Motorola 680X0 series was the first to implement this design, resulting in significant memory savings compared to traditional one-level systems. However, this approach can lead to slower performance due to additional memory access and increased complexity in control-unit organization.

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83 views9 pages

Nano Programming

Nanoprogramming introduces a two-level control memory system in processors, consisting of microcontrol memory (μCM) for microinstructions and nanocontrol memory (nCM) for nanoinstructions, enhancing efficiency and reducing control memory size. The Motorola 680X0 series was the first to implement this design, resulting in significant memory savings compared to traditional one-level systems. However, this approach can lead to slower performance due to additional memory access and increased complexity in control-unit organization.

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Nano programming

• In most microprogrammed processors, an instruction fetched from


memory is interpreted by a microprogram stored in control memory
(CM).
However, in nanoprogrammed processors, there are two levels of
control memory:
• Microcontrol memory (μCM or pCM): stores microinstructions.
• Nanocontrol memory (nCM): stores nanoinstructions that directly
control the hardware.
• Nanoprogramming was first incorporated in the Motorola 680X0 (1994)
• µCM - Hₘ × Wₘ
• nCM - Hₙ × Wₙ
• Where Hₘ is the number of microinstructions stored in CM and Wₘ is the width
in bits of each microinstruction
• The advantage of this two-level control design technique is that it can
reduce the total size S2 = Hₘ × Wₘ + Hₙ × Wₙ of the control memories,
Typically, the microprograms are encoded in a narrow
vertical format so that although Hₘ is large, Wₘ is small.

A two-level control system is better than a one-level


system because:
• It reduces total control memory size.
• Microinstructions can be reused with different
nanoinstructions, increasing efficiency.

If one nanoprogram can interpret many


microinstructions, then Hₙ can be kept relatively small so
that S2 < S1 = Hₘ × Wₘ
Advantages:
- The potential for reducing the total size of the control
memories is the main reason for the use of
nanoprogramming in the 680X0 series.
- Another advantage is the greater design flexibility that
results from loosening the bonds between instructions
and hardware with two intermediate levels of control
rather than one.
Disadvantage:
- The main disadvantages of the two-level approach are a
loss of speed due to the extra memory access for nCM
and a more complex control-unit organization
Control memory models
A one-level conventional CM is assumed to store Hm
horizontal microinstructions each with a format
consisting of N control bits and ⌈log⁡2Hm⌉ next-address
bits. The size of this memory is therefore
S₁ = Hₘ (N + ⎡log₂ Hₘ⎤)
In place of the latter, each
microinstruction in μCM
contains a ⌈log2​Hn​⌉ bit
address to specify any
nanoinstruction location in
nCM. It is assumed that little
or no branching takes place
among nanoinstructions, so
no explicit address bits are
included in the model of nCM.
Thus the size of the two-level
control store is

S₂ = Hₘ (⎡log₂ Hₘ⎤ + ⎡log₂ Hₙ⎤)


+ N Hₙ
Suppose that all the control-bit patterns in nCM are
different so that each represents a unique control state
associated with the given instruction set. We can write
Hₙ = r Hₘ
where r is the ratio of the number of unique control
states to the total number Hₙ of control states needed to
implement all instructions.
S₂ = Hₘ (2 ⎡log₂ Hₘ⎤ + ⎡log₂ r⎤ + r N)
The following parameters are cited for the 68000
processor design:
N = 70, Hₘ = 650, and r = 0.4, so that Hₙ = 260.
Substituting these values into equations we obtain S₁ =
52,450 and S₂ = 30,550.
Consequently, the use of nanoprogramming saves a total
of
52,450 − 30,550 = 21,850 bits of control storage, which
is 42 percent of S₁. In general, two levels of control
memory require less memory space if S₂ < S₁.

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