Digital Electronic Circuits
(EC2L004)
Lecture 9: Combinational Logic –
Part II
Multiplexers/Data selectors
• A multiplexer is a combinational circuit that selects
binary information from one of many input lines
and directs it to a single output line.
• The selection of a particular input line is controlled by
a set of selection lines.
• Normally, there are 2n input lines and n selection lines
whose bit
combinations determine which input is selected.
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4x1 multiplexer
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Quadruple two-to-one-line multiplexer
• Multiplexer circuits can be combined with common
selection
inputs to provide multiple-bit selection logic.
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Boolean Function Implementation
• Implement the following function using 8x1 mux and
also with
4x1 mux.
F (x, y, z) = ∑(1, 2, 6, 7)
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Boolean Function Implementation
• Implement the following function using 8x1
mux
F (A, B, C, D) = ∑(1, 3, 4, 11, 12, 13,
14, 15)
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Boolean Function Implementation: Summary
• Step 1: Complete the truth table from the SOP.
• Step 2: The first n – 1 variables in the table are
applied to the selection inputs of the multiplexer.
• Step 3: For each combination of the selection
variables, we evaluate the output as a function of
the last variable.
• Step 4: Apply these values to the data input in
proper order.
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Demultiplexer
• Multiplexer (MUX)
• Routes one of many inputs to a
single output
• Also called a selector
contr
• Demultiplexer (DEMUX) ol
• Single data input; n control
inputs (“selects”); 2n outputs
• Single input connects to one
of 2n
outputs
• “Selects” decide which
output is connected to the
input
contr
ol
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3x8 Demux
• The input is called an
“enable” (G)
0
1
2 3:8 Decoder:
3 Out0 = G S2' S1'
G 3:
4 S0'
8
Demux 5
6 Out1 = G S2' S1'
S0
7
Out2 = G S2' S1
S2 S1 S0'
S0 Out3 = G S2' S1 S0
Out4 = G S2 S1'
C
S0'
A B Out5 = G S2 S1'
S0 Out6 = G S2
S1 S0' Out7 = G
S2 S1
S0
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | 9
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Demultiplexers: Implemtation
G Out
0
S
Out G
Ou 0
1:2 1 t
demux
Out
1:2 1
Decoder:
Out0 = G Out
S' Out1 = G 2
S
Out
2:4
3
Decoder: Out0 =
G S1' S0'
Out1 = G S1'
2:4
S0 demux
Out2 = G S1
S0' Out3 = G S1 S0
S1 S0
[30/01/2024, IIT BBS] | [Srinivas Boppu]
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| [SES] | 10
Demultiplexer as logic block
• A n:2n demux can implement any function of n
variables
• Use variables as select inputs
• Tie enable input to logic 1
• Sum the appropriate minterms (extra OR gate)
0 A'B'
1 C'
2 A'B'
1 3: 3 C
A'BC
Demux
8 5 '
4 6 A'B
7 C demultiplexer
S2 S1 AB' “decodes”
S0 C'
AB' appropriate
A C C minterms from the
B ABC
' control signals
ABC
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | 11
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Demultiplexer as logic block
F1 = A'BC'D + A'B'CD +
ABCD
F2 = ABC'D' +
0 A'B'C'
ABC F3 = 1 A'B'C'
D'
2 D F
(A'+B'+C'+D') 3 A'B'C 1
4 D'
5 A'B'C
6 D
7 A'BC'
Enable = 4:1 D'
Demux
6 F
1 9 A'BC'
8 1 D 2
0 A'BCD
1 '
1 A'BCD
1 AB'C'
2 D' F
1 AB'C' 3
3 D
A B C1 AB'CD
D 4 '
1 AB'C
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[EC2L004] 5 D
Cascading demultiplexers
• 5:32
0 A'B'C'D' 0
demux 1 E' 1
2 2
3: 3
Demux
8 A'BC'DE'
5 3
4 6 :
7 7
8
S2 S1 S2 S1
0
2: 1 S0 S0 3
F Demux D
4
3 e
S1
2 m
0 0 AB'C'D'
S0 1 u1
x E'
2 2
A 3: 3 3:8 43
B Demux
8 Demux 54
4 5
5 66
7
6 ABCD 7 AB'CD
E S2 S1 E
S2 S1 S0
S0
C D C D
E E
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Decoders
• A decoder is a combinational circuit that converts
binary
information from n input lines to an 2n unique
output lines.
• Some Applications:
• Microprocessor memory system: selecting different
banks of memory.
• Microprocessor I/O: Selecting different devices.
• Memory: Decoding memory addresses (e.g. in ROM).
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | 14
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Three-to-Eight Line Decoder
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Three-to-Eight Line Decoder
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2-to-4-line DECODER with Enable
• The decoder is enabled when E = 0. The output
whose value
= 0 represents the minterm is selected by inputs A
and B.
• The decoder is inactive when E = 1 -> D0 …D3 = 1
• A Decoder with enable input is called a
decoder/demultiplexer.
• Demultiplexer receives information from a single
line and directs it to the output lines.
0
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2-to-4-line DECODER with Enable
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4x16 decoder with two 3x8 decoders
• When w = 0, the top decoder is enabled and the bottom is
disabled.
• Top decoder generates 8 minterms 0000 to 0111, while
the bottom decoder outputs are 0’s.
• When w = 1, the top decoder is disabled and the bottom is
enabled.
• Bottom decoder generates 8 minterms 1000 to 1111,
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | 19
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Implementation of Full Adder using 3x8
Decoder
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | 20
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Encoders
• An encoder is a digital circuit that performs the
inverse operation of a decoder. An encoder has 2n
(or fewer) input lines and n output lines.
• It is assumed that only one input has a value of 1 at
any given
point in time.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | 21
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Encoders (Contd.)
• The encoder can be implemented with OR gates
whose
inputs are determined directly from the truth
table.
• Two problems
• What if two inputs are active simultaneously?
• Output with all 0’s generated when all the inputs are
0; but this
same as when D0 is equal to 1.
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Priority Encoder
• A priority encoder is an encoder circuit that includes
the priority function. The operation of the priority
encoder is such that if two or more inputs are equal
to 1 at the same time, the input having the highest
priority will take precedence.
• Input D3 has the highest
priority.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] |
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23
Priority Encoder (Contd.)
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Priority Encoder (Contd.)
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• Disclaimer: Demultiplexer slides are copied from
different open sources on the internet, and I do not
claim the ownership of these slides.
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