ECE4101 (VLSI Design)

Dr. Sheikh Md. Rabiul Islam

ECE Dept, KUET , Bangladesh

PROGRAMMABLE
LOGIC DEVICES (PLD)

1
 Suplementary reading Books
• Digital Logic Circuit Analysis and Deign
– Authors:
– Victor R. Nelson
– H. Troy Nagle
– J. David Irwin
– Bill D. Carroll

• Chapter 5

2
 Why Programmable Logic?
• Facts:
– It is most economical to produce an IC in large
volumes
– Many designs required only small volumes of ICs
• Need an IC that can be:
– Produced in large volumes
– Handle many designs required in small volumes
• A programmable logic part can be:
– made in large volumes
– programmed to implement large numbers of different
low-volume designs
3
Programmable Logic - Additional Advantages
• Many programmable logic devices are field-
programmable, i. e., can be programmed outside of
the manufacturing environment
• Most programmable logic devices are erasable and
reprogrammable.
– Allows “updating” a device or correction of errors
– Allows reuse the device for a different design - the ultimate
in re-usability!
– Ideal for course laboratories
• Programmable logic devices can be used to
prototype design that will be implemented for sale in
regular ICs.
– Complete Intel Pentium designs were actually prototype with
specialized systems based on large numbers of VLSI
programmable devices! 4
 Programming Technologies
• Programming technologies are used to:
– Control connections
– Build lookup tables
– Control transistor switching
• The technologies
– Control connections
• Mask programming
• Fuse
• Antifuse
• Single-bit storage element
5
 Technology Characteristics
• The technologies (continued)
– Build lookup tables
• Storage elements (as in a memory)
– Transistor Switching Control
• Stored charge on a floating transistor gate
– Erasable
– Electrically erasable
– Flash (as in Flash Memory)
• Storage elements (as in a memory)

6
 Technology Characteristics
• Permanent - Cannot be erased and reprogrammed
• Mask programming
• Fuse
• Antifuse

• Reprogrammable
– Volatile - Programming lost if chip power lost
• Single-bit storage element
– Non-Volatile
• Erasable
• Electrically erasable
• Flash (as in Flash Memory)
– Build lookup tables
• Storage elements (as in a memory) 7
 PLD
 An IC that contains large numbers of gates, flip-flops,
etc. that can be configured by the user to perform
different functions is called a Programmable Logic
Device (PLD).
 The internal logic gates and/or connections of PLDs can
be changed/configured by a programming process.
 One of the simplest programming technologies is to use
fuses. In the original state of the device, all the fuses are
intact.
 Programming the device involves blowing those fuses
along the paths that must be removed in order to obtain
the particular configuration of the desired logic function.

8
 PLD
• Problems of using standard ICs in logic design:

– require hundreds or thousands of these ICs

– require a considerable amount of circuit board space

– require a great deal of time and cost in inserting,

soldering, and testing

– require to keep a significant inventory of ICs

9
 PLD
• Advantages of reducing the no. of ICs using PLD:

– less board space

– fewer printed circuit boards
– smaller enclosures
– lower power requirements (i.e., smaller power supplies)
– faster and less costly assembly processes
– higher reliability (fewer ICs and circuit connections =>
easier troubleshooting)
– availability of design software

10
 PLD
Types of Programmable Logic Devices
• SPLDs (Simple Programmable Logic Devices)
– ROM (Read-Only Memory)
– PLA (Programmable Logic Array)
– PAL (Programmable Array Logic)
– GAL (Generic Array Logic)
• CPLD (Complex Programmable Logic Device)
• FPGA (Field-Programmable Gate Array)

11
 PLD
• The first three varieties are quite similar to
each other:
– They all have an input connection matrix, which
connects the inputs of the device to an array of
AND-gates.
– They all have an output connection matrix, which
connect the outputs of the AND-gates to the inputs
of OR-gates which drive the outputs of the device.

• The gate array is significantly different and

will be described later.
12
 PLD
• The differences between the first three categories
are these:
– In a ROM, the input connection matrix is hardwired.
The user can modify the output connection matrix.
– In a PAL/GAL the output connection matrix is
hardwired. The user can modify the input connection
matrix.
– In a PLA the user can modify both the input connection
matrix and the output connection matrix.

13
General structure of PLDs.

14
 Tristate Buffer

A tristate buffer can output 3 different
values:
 Logic 1 (high)
 Logic 0 (low)
 High-Impedance
control

input output

Fall 2010 ECE 331 - Digital System Design 15

 Tristate Buffers
Enable

Fall 2010 ECE 331 - Digital System Design 16

 Buffer/inverter

(a) Symbol. (b) Logic equivalent.

17
 Programming by blowing
fuses.

(a) Before programming. (b) After programming.

18
OR - PLD Notation

19
AND - PLD Notation

20
21
 ROM, PAL and PLA Configurations
Fixed Programmable
Inputs Programmable Outputs
AND array
(decoder) Connections OR array

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array

(c) Programmable logic array (PLA) device

22
Read-Only Memory (ROM)

23
 Read-Only Memory (ROM)

Fixed Programmable
Inputs Programmable Outputs
AND array
(decoder) Connections OR array

— The array of AND gates is fixed programmed to

generate any product terms of the input variables.
— The product terms are then connected to OR gates to

provide the sum of products for the required Boolean

functions.

24
PROM Notation

25
 ROM as a Memory
• Read Only Memories (ROM) or Programmable Read
Only Memories (PROM) have:
– N input lines,
– M output lines, and
– 2N decoded minterms.
• Can be viewed as a memory with the inputs as
addresses of data (output values),
– hence ROM or PROM names!

27
 Using a PROM for logic design

(a) Truth table. (b) PROM realization.

28
 ROM
• ROM
 A decoder
 A set of programmable D7 X X X
D6
OR’s D5 X X
D4 X
A A2 D3 X
D2
B A1 D1 X X
A0 D0 X
C

F3 F2 F1 F0

29
 ROM
• Decoder
 Produces minterms
• ORs 0
1
A‘B’C’D’
A ‘B’C’D
F1
 Produce SOP’s 2
3
A‘B’CD’
A‘B’CD
A S3 4 A‘BC’D’
5 A‘BC’D
S2
B 4:16
6 A‘BCD’
7 A‘ BCD
S1 dec
C 8 A B’C’D’ F2
9 A B’C’D
S0 10 A B’CD’
D
11 A B’CD
12 A B C’D’
13 A B C’D
14 A B C D’ F3
15 AB C D

Enb

30
 Example

• Find a ROM-based circuit

implementation for:
– f(a,b,c) = a’b’ + abc
– g(a,b,c) = a’b’c’ + ab + bc
– h(a,b,c) = a’b’ + c
• Solution:
– Express f(), g(), and h() in m() format (use
truth tables)
– Program the ROM based on the 3 m()’s
31
 Example
– There are 3 inputs and 3 outputs, thus we
need a 8x3 ROM block.
• f = m(0, 1, 7)
• g = m(0, 3, 6, 7)
• h = m(0, 1, 3, 5, 7)

a 0
1
3-to-8 2
b 3
decoder 4
5
c 6
7

f g h
32
 Example: 32x8 ROM
A ROM has an internal decoder and n OR gates
• 32 words of 8 bits each
– 32*8=256 programmable internal connections
– 5 inputs decoded into 32 distinct outputs by 5x32
decoder
–Each of 8 OR gates have 32 inputs

33
Example: 32x8 ROM
programmable
intersection:
crosspoint switch
•Two conditions
– close: two lines
are connected
– open: two lines
are disconnected
•Implemented by
fuse
– normally connects
the two points
– opened or “blown”
by applying a
high-voltage pulse
A7(I4,I3,I2,I1,I0)
=Σ(0,2,3,…,29)

34
Example: PROM
𝑸 𝟑= 𝑨𝑩+ 𝑪 𝑫 , 𝑸𝟐= 𝑨𝑩 𝑪

𝑸 𝟏= 𝑨𝑩 𝑪 𝑫+ 𝑨 𝑩 𝑪 𝑫 ,
𝑸 𝟎= 𝑨+𝑩 𝑫+𝑪 𝑫

35
 ROM as Memory
• Read Example: For input (A2,A1,A0) = 011, output is
(F0,F1,F2,F3 ) = 0010.
• What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?

Address 8x4 ROM

D0 X X X 0 1 1 0 1
D1
1 0 0 0 0
D2 X X
D3 X 2 1 0 0 1
A A2 D4 X A[2:0] F[3:0]
D5 3 0 0 1 0
B A1 D6 X X
A0 D7 X 3 4 0 0 0 0 4
C
5 1 0 0 0
6 0 0 1 1
7 0 1 0 0
F0 F1 F2 F3
36
Programmable Logic Array (PLA)

37
 PLA
Programmable Programmable Programmable Programmable
Inputs Outputs
Connections AND array Connections OR array

(c) Programmable logic array (PLA) device

 In PLAs, instead of using a decoder as in PROMs, a

number (k) of AND gates is used where k < 2n, (n
is the number of inputs).
 Each of the AND gates can be programmed to
generate a product term of the input variables and
does not generate all the minterms as in the ROM.

38
 PLA
 The AND and OR gates inside the PLA are initially
fabricated with the links (fuses) among them.
 The specific Boolean functions are implemented in sum of
products form by opening appropriate links and leaving the
desired connections.
 A block diagram of the PLA is shown in the figure. It
consists of n inputs, m outputs, and k product terms.

39
 PLA
 The product terms constitute a group of k AND gates each of
2n inputs.
 Links are inserted between all n inputs and their complement
values to each of the AND gates.
 Links are also provided between the outputs of the AND gates
and the inputs of the OR gates.
 Since PLA has m-outputs, the number of OR gates is m.
 The output of each OR gate goes to an XOR gate, where the
other input has two sets of links, one connected to logic 0 and
other to logic 1. It allows the output function to be generated
either in the true form or in the complement form.
 The output is inverted when the XOR input is connected to 1
(since X ⊕ 1 = X/). The output does not change when the XOR
input is connected to 0 (since X ⊕ 0 = X).
40
 PLA
 Thus, the total number of programmable links is 2n x k + k x
m + 2m.
 The size of the PLA is specified by the number of inputs (n),
the number of product terms (k), and the number of outputs
(m), (the number of sum terms is equal to the number of
outputs).

Advantages of PLA

 Efficient in terms of area needed for

implementation on an IC chip
 Often included as part of larger chips such as
microprocessors
 Programmable AND and OR gates
41
 PLA Logic Implementation
Implement: F1(A, B, C) = Σ (0, 1, 2, 4); F2(A, B, C) = Σ (0,
5, 6, 7)
1. Simply both the true and complement of the functions in sum of products

2. Find the combination with

minimum number of
product terms
F1=(AB+AC+BC)’
F2=AB+AC+A’B’C’

3. Obtain the PLA

programming table

4. Draw the circuit diagram of

PLA using AND-OR plane

42
PLA Logic Implementation
Implement: F1(A, B, C) = Σ (0, 1, 2, 4); F2(A, B, C) = Σ (0,
5, 6, 7)

4. Draw the circuit diagram of

PLA using AND-OR plane

43
PLA Logic
Implementation Unprogrammed device
• Alternative representation
for
high fan-in structures
• Short-hand notation so we
don't
have to draw all the wires!
• X at junction indicates a
connection
A B C D Programmed device

Notation for implementing AB

AB
F0 = A B + A B
CD
F1 = C D + C D
CD

AB+AB CD+CD
44
 Example: PLA Logic Implementation
PLA as ROM: A B C Bit stored in memory
Multiple functions of A, B, C
ABC
F1 = A B C
A

F2 = A + B + C B

C
F3 = A B C
A

F4 = A + B + C B

C
F5 = A  B  C
ABC

F6 = A  B  C ABC

ABC

ABC

ABC

ABC

ABC

Address F1 F2 F3 F4 F5 F6
45
Example: PLA Logic Implementation

Figure; 3-input, 2-output

PLA with 4 product terms
46
 Review of Boolean Algebra
A Z A B Z A B Z A B Z A B Z
0 1 0 0 0 0 0 0 0 0 1 0 0 1
1 0 0 1 1 0 1 0 0 1 0 0 1 1
1 0 1 1 0 0 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0
NOT OR AND NOR NAND
Truth Table Truth Table Truth Table Truth Table Truth Table
Z A Z A  B Z = AB Z = A +B Z = AB


47
PLAs: NOR-NOR Implementation
PLA structures
Programmable Logic Array structures provide a logical and
compact method of implementing multiple SOP (Sum of
Products) or POS expressions

(a) AND-OR logic

(b) NOR-based logic

48
PLAs: NOR-NOR Implementation
Pseudo-NMOS
 full nMOSlogic array
• replace pMOSarray with single pull up
transistor
• Ratioed Logic
–requires proper txsize ratios•
• Advantages
–less load capacitance on input signals
•faster switching–
-fewer transistors
•higher circuit density
• Disadvantage
–pull up is always on
•significant static power dissipation Fig. nMOS generic
–VOL> 0 pseudo-nMOS logic
gatepseudo

49
PLAs: NOR-NOR Implementation
Pseudo-NMOS

Fig. pseudo-nMOS NAND and

Fig. pseudo-nMOS NOR
inverter

50
 PLAs: NOR-NOR Implementation

NOR function in programmable logic

Truth
Table:
X1 X2 Z
Xi = 0 turns transistor OFF (transistor = open circuit) 0 0 1
Xi = 1 turns transistor ON (transistor shorts Z to ground/0)
+V pulls Z up to 1 if not shorted to ground 0 1 0
1 0 0
1 1 0

51
PLAs: NOR-NOR Implementation

NOR function in programmable logic

𝐹 0=¿

52
PLAs: NOR-NOR Implementation

53
 PLAs: NOR-NOR Implementation

PLA implements SOP forms

𝐹 0= 𝐴 𝐵+ 𝐴 𝐶

products sum
Equivalent
AND-OR form

54
 PLA Logic Implementation
 Example: NOR-NOR PLA

De-Morgan’s Law:
𝐴 . 𝐵= 𝐴+ 𝐵
𝐴+ 𝐵= 𝐴 𝐵

55
PLA Logic Implementation
 Example: Full Adder using NOR-NOR PLA

s abc  abc  abc  abc

cout ab  bc  ac

56
 PLA Logic Implementation
 Example: Full Adder using nMOS NOR_NOR PLA

s abc  abc  abc  abc 𝑉 𝑠𝑠

𝑉 𝑠𝑠
𝑉 𝑑𝑑
𝑉 𝑑𝑑
cout ab  bc  ac

𝑉 𝑠𝑠
𝑉 𝑠𝑠

57
PLAs: NOR-NOR Implementation
PLA structures
Programmable Logic Array structures provide a logical and
compact method of implementing multiple SOP (Sum of
Products) or POS expressions

Most PLA structures employ pseudo-NMOS NOR

gates using a P-channel device in place of the NMOS
depletion load.
58
PLAs: NOR-NOR Implementation
PLA structures 𝑉 𝑑𝑑 𝑉 𝑑𝑑 𝑉 𝑑𝑑

𝑉 𝑑𝑑

𝑉 𝑑𝑑

𝑉 𝑑𝑑
𝑉 𝑑𝑑

• A regular layout is employed, with columns for inputs and

outputs and rows for intermediate expressions.

59
PLAs (Contd)

PLA structure using Pseduo-NMOS NOR-NOR

𝑉 𝑑𝑑

𝑉 𝑑𝑑

• Layout is simply a matter of selecting and placing rectangular cells

from a limited set.

60
PLAs (Contd)

PLA structure

• Conversion to sticks is straight forward with opportunities for

further optimization.

61
PLAs (Contd)
Design a PLA circuit using
Pseduo-NMOS NOR-NOR to
realize the following sum
of product functions:

62
Programmable Array
Logic (PAL)

63
 (PAL)
The steps for PAL design and implementation are given
below:

64
 (PAL)
Advantages of PALs
* Ease of design
* Performance
* Reliability
* Cost Savings
Characteristics of PALs
COMBINATIONAL:
* Number of inputs
* Number of outputs
* Number of product terms per
output
* Speed
* Power consumption
* Reprogrammable ?
REGISTERED:
* + Number of Registers

65
 (PAL)

Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array

(b) Programmable array logic (PAL) device

— Only the AND gates are programmable.

— The PAL is easier to program, but is not as

flexible as the PLA.

66
PALs and PLAs
• What is difference between Programmable Array Logic (PAL)
and
Programmable Logic Array (PLA)?
• PAL concept — implemented by Monolithic Memories
- AND array is programmable, OR array is fixed at
fabrication

A given column of the OR array

has access to only a subset of
the possible product terms

PLA concept — Both AND and OR arrays are programmable

67
 Programmable Array Logic (PAL)

• The PAL is the opposite of the ROM, having a

programmable set of ANDs combined with fixed
ORs.

• Disadvantage
– ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.

• Advantages
– For given internal complexity, a PAL can have larger
N and M
– Some PALs have outputs that can be complemented,
adding POS functions
68
PALs and PLAs
• Of the two organizations the PLA is the most
flexible
– One PLA can implement a huge range of logic functions
– BUT many pins; large package, higher cost
• PALs are more restricted / you trade number of OR
terms vs number of outputs
– Many device variations needed
– Each device is cheaper than a PLA

69
A simple input and output PAL device.

inputs

1st output
section

2nd output Only functions with

section at most four
products can be
implemented
3rd output
section

4th output
section

70
 PAL Logic
Implementation(Example)
W = ABC + A’B’C
X = AB + ABC

71
 PAL Logic
Implementation(Example)
W = ABC + CD
X = ABC + ACD + ACD + BCD
Y = ACD + ACD + ABD

72
Example: PAL
𝑸 𝟑= 𝑨𝑩+ 𝑪 𝑫 , 𝑸𝟐= 𝑨𝑩 𝑪

𝑸 𝟏= 𝑨𝑩 𝑪 𝑫+ 𝑨 𝑩 𝑪 𝑫 ,
𝑸 𝟎= 𝑨+𝑩 𝑫+𝑪 𝑫

73
PLA,PAL and ROM Logic
Implementation
Design a PLA, PAL and ROM at a gate level to realize the following sum of
product functions:
X(A,B,C)=A.B+A.B.C+A.B.C
Y(A,B,C)=A.B+A.B.C
Z(A,B,C)=A+B

74
PLA,PAL and ROM Logic
Implementation
Design a PLA, PAL and ROM at a gate level to realize the following sum of product functions:
X(A,B,C)=A.B+A.B.C+A.B.C
Y(A,B,C)=A.B+A.B.C
Z(A,B,C)=A+B

ROM Implementation:

75
PLA,PAL and ROM Logic
Implementation
Design a PLA, PAL and ROM at a gate level to realize the following sum of product functions:
X(A,B,C)=A.B+A.B.C+A.B.C
Y(A,B,C)=A.B+A.B.C
Z(A,B,C)=A+B

PAL Implementation:

76
PLA,PAL and ROM Logic
Implementation
Design a PLA, PAL and ROM at a gate level to realize the following sum of product functions:
X(A,B,C)=A.B+A.B.C+A.B.C
Y(A,B,C)=A.B+A.B.C
Z(A,B,C)=A+B

PLA Implementation:

77
PLA,PAL and ROM Logic
Implementation
Example: The internal connection diagram for a PLA is given
below.
(a) Write the equations realized by the PLA.
(b) Specify the truth table for a ROM which would realize the
same function

78
PLA,PAL and ROM Logic
Implementation
Solution:
(a)
X = A'BD + C'D + AB' + AB'C'D'
Y = A'BD + BCD + AB'
Z = A'BD + BCD + ABC + AB'C'D'

79
PLA,PAL and ROM Logic
Implementation
Solution:(b) ROM table is given below. Realization by ROM does not require
any minimization. All states are simply mapped as defined in the state table. Size
of the ROM would be 16x4 bits as shown in the block diagram below.

X = A'BD + C'D + AB' + AB'C'D'

Y = A'BD + BCD + AB'
Z = A'BD + BCD + ABC + AB'C'D'

80
81
82
PLA Extra circuitry: Macrocell
Select Enable

f1
Flip-flop
D Q

Clock

To AND plane

For additional flexibility, extra circuitry is added at the output of each OR gate.
This is also referred to macrocell.

83
PLA Extra circuitry : Macrocell

 Flip-flops store the value produced by the OR gate output at a particular

point and can hold it indefinitely.

 Flip-flop output is controlled by the clock signal. On 0-1 transition of

clock, flip-flop stores the value at its D input and latches the value at Q
output.

 2-to-1 multiplexer selects an output from the OR gate output or the flip-flop
output. Tri-state buffers are placed between multiplexer and the PAL output.

 Multiplexer’s output is fed back to the AND plane in PAL, which allows the
multiplexer signal to be used internally in the PAL. This facilitates the
implementation of circuits that have multiple stages (levels or logic gates).

84
 Example: FSM Implementation using
Microcell

P & Q – are inputs

y2 & y1 are the states
Z is the output

85
GAL

A GAL implements a combinational as well a sequential

circuit of (n + m) inputs and outputs. The GAL has a
macro-cell at each output stage of the SOPs.

"Digital Principles and Design", Raj Kamal, Pearson Education,

86
Generic Array Logic (GAL)

• A GAL implements a combinational as well a

sequential circuit of (n + m) inputs and outputs.
The GAL has a macro-cell at each output stage of
the SOPs.
• A PAL like device with an like erasing ability and a
programmable output stage as a combinational or
sequential circuit.
• GAL cell provides a more flexible output stage then
simply a tristate NOT or a D-FF plus tristate NOT
like in the 16 L8 and 16R8, respectively.

"Digital Principles and Design", Raj Kamal, Pearson Education,

87
Generic Array Logic (GAL)

• Flexible means programmability using fuse

links at the output stage either as (i) active
‘1’, or (ii) active ‘0’, or (iii) standby state
either ‘0’ or ‘1’ or ‘tristate’ or ‘tristate not’,
or (iv) the output feedback as such or with
complement, or (v) the output feedback to
the present stage input (iv) the output of
previous stage given as a succeeding stage
input as given in a ripple counter or ring
counter or Johnson counter.

"Digital Principles and Design", Raj Kamal, Pearson Education,

88
Generic Array Logic (GAL)

• Erasable like an and so that it becomes

array that is usable again
• Programmable logic device (PLD) as PAL as
well as Registered PAL
• Flexibility to convert a PLD from a
combinational circuit device, like PAL16L8 to
a sequential circuit device, like PAL 16R8 (or
21R8 where maximum inputs can be 20
corresponding to 40 columns)

"Digital Principles and Design", Raj Kamal, Pearson Education,

89
GAL Macro-cell Selectable options

(i) a feedback to input as addition input from a

present stage or a neighboring stage,
(ii) a complementary output,
(iii) a tristate output, and
(iv) a registered output

"Digital Principles and Design", Raj Kamal, Pearson Education,

90
GAL Segment: Output Logic Macrocell
(OLMC)
1) Register
2) Feedback
3) I/O: e.g. 12 input pins, 10 I/O pins
4) -S1S0=10 : FF is bypassed, output
from OR, inverted and fed back to AND
-S1S0=01 : output from FF, not
inverted and fed back to AND
-S1S0=00 : dashed lines
OR

-When tri-state buffer

is in high-Z mode,
OR and FF are
disconnected and
pin can be used To AND
for input

"Digital Principles and Design", Raj Kamal, Pearson Education,

91
GAL Segment: Output Logic Macrocell
(OLMC)
1) Register
2) Feedback
3) I/O: e.g. 12 input pins, 10 I/O pins
4) -S1S0=10 : FF is bypassed, output
from OR, inverted and fed back to AND
-S1S0=01 : output from FF, not
inverted and fed back to AND
-S1S0=11 : dashed lines

OR
-When tri-state buffer
is in high-Z mode,
OR and FF are
disconnected and
pin can be used
for input To AND

"Digital Principles and Design", Raj Kamal, Pearson Education,

92
GAL Segment: Output Logic Macrocell
(OLMC)

• PROM programs OR links, PAL AND links and

PLA AND-OR both links
• Output stage can have provision for output of
variable or complement form or for tristate
output
• Output stage can have provision for feedback
to AND arrays trough tristate gates
• Output stage can have provision for output
through edge clocked D-FF
• Registered Sequential circuit Feedback of IO
from same or previous stage as in a register
or counter
• GAL has a macro-cell having three MUX using
which outputs and feedbacks are
programmed
"Digital Principles and Design", Raj Kamal, Pearson Education,
93
Sequential Programmable
Devices

94
Sequential Programmable Devices
Three major types of PLD
 Sequential (or simple) programmable logic
device (SPLD)
• field-programmable logic sequencer (FPLS)
 Complex programmable logic device (CPLD)
 Field programmable gate array (FPGA)
Sequential programmable devices
 combinational PLD + flip-flops
 perform a variety of sequential-circuit
functions
Many commercial vendor-specific variants and
internal logic of these devices is too complex to be
shown here
95
Sequential(or Simple) Programmable logic
Devices

Fig. Block diagram of SPLD

• SPLD includes flip-flops and AND-OR array
–flip-flops connected to form a register
–FF outputs could be included in product terms of AND
array
–Field-programmable logic sequencer (FPLS)
• first programmable device developed, FF may be of D or JK type
• not succeed commercially due to too many programmable
connections
–Combinational PAL together with D flip-flops: most used
96
 SPLD: Macrocell

Macrocell: a section of an SPLD

 a circuit containing a sum-of-products combinational
logic function and an optional flip-flop
 a typical SPLD contains 8-10 macrocells
 Features:
 programming AND array
 use or bypass the flip-flop
 select clock edge polarity
 preset or clear for the register
 complement an output

 FF is connected to a common clock

 OE (output enable) signal also
controls all the three-state buffers
 FF output is fed back to PAL inputs

97
FPGA

A field programmable logic array (FPLA) only

those minterms that are needed are generated. Also,
each is generated only once, even though it may appear
multiple times in the output expressions.

98
 FPGA Classification

FPGA
types

Implementation Logic Implementation Interconnect Technology

Architecture

Symmetrical Look Up table Static Ram

Array Multiplexer Antifuse
Row based Array based
E/EPROM
Hierarchical PLD PLD Block
Sea of Gates NAND Gates

99
FPGA
architecture
The FPGA consists of 3 main structures:
1. Programmable logic structure,
2. Programmable routing structure, and
3. Programmable Input/Output (I/O).

100
FPGA
architecture
1. Programmable logic structure
 The programmable logic structure FPGA consists of a 2-dimensional
array of configurable logic blocks (CLBs).

101
FPGA
architecture
1. Programmable logic structure
 Each CLB can be configured (programmed) to implement any
Boolean function of its input variables. Typically CLBs have
between 4-6 input variables. Functions of larger number of
variables are implemented using more than one CLB.
 In addition, each CLB typically contains 1 or 2 FFs to allow
implementation of sequential logic.
 Large designs are partitioned and mapped to a number of
CLBs with each CLB configured (programmed) to perform a
particular function.
 These CLBs are then connected together to fully implement
the target design. Connecting the CLBs is done using the
FPGA programmable routing structure.

102
FPGA
architecture
2. Programmable routing structure
To allow for flexible interconnection of CLBs, FPGAs have 3
programmable routing resources:
1. Vertical and horizontal routing channels which consist of
different length wires that can be connected together if needed.
These channel run vertically and horizontally between columns
and rows of CLBs as shown in the Figure.
2. Connection boxes, which are a set of programmable links
that can connect input and output pins of the CLBs to wires of
the vertical or the horizontal routing channels.
3. Switch boxes, located at the intersection of the vertical and
horizontal channels. These are a set of programmable links that
can connect wire segments in the horizontal and vertical
channels.
103
FPGA
architecture
2. Programmable routing structure

104
FPGA
architecture
3. Programmable Input/Output (I/O)
 These are mainly buffers that can be configured either as
input buffers, output buffers or input/output buffers.
 They allow the pins of the FPGA chip to function either as
input pins, output pins or input/output pins.
Programable I/Os

105
FPGA
architecture

106
FPGA
architecture

FPGA architecture

107
FPGA
architecture

108
What does a logic cell do?
• The logic cell architecture varies between different device
families.
• Each logic cell combines a few binary inputs (typically
between 3 and 10) to one or two outputs according to a
Boolean logic function specified in the user program .
• In most families, the user also has the option of registering
the combinatorial output of the cell, so that clocked logic
can be easily implemented.
• Cell's combinatorial logic may be physically implemented
as a small look-up table memory (LUT) or as a set of
multiplexers and gates.
• LUT devices tend to be a bit more flexible and provide
more inputs per cell than multiplexer cells at the expense of
propagation delay.

109
what does 'Field Programmable'
mean?
• Field Programmable means that the FPGA's function is
defined by a user's program rather than by the manufacturer
of the device.
• A typical integrated circuit performs a particular function
defined at the time of manufacture. In contrast, the FPGA's
function is defined by a program written by someone other
than the device manufacturer.
• Depending on the particular device, the program is either
'burned' in permanently or semi-permanently as part of a
board assembly process, or is loaded from an external
memory each time the device is powered up.
• This user programmability gives the user access to complex
integrated designs without the high engineering costs
associated with application specific integrated circuits.

110
How are FPGA programs
created?
• Individually defining the many switch connections and cell
logic functions would be a daunting task.
• This task is handled by special software. The software
translates a user's schematic diagrams or textual hardware
description language code then places and routes the
translated design.
• Most of the software packages have hooks to allow the user
to influence implementation, placement and routing to
obtain better performance and utilization of the device.
• Libraries of more complex function macros (eg. adders)
further simplify the design process by providing common
circuits that are already optimized for speed or area.

111
FPGA

 FPGA applications:-
i. DSP
ii. Software-defined radio
iii. Aerospace
iv. Defense system
v. ASIC Prototyping
vi. Medical Imaging
vii. Computer vision
viii.Speech Recognition
ix. Cryptography
x. Bioinformatic
xi. And others.
112
CPLD
Chips containing PLDs are limited to modest sizes,
typically supporting number of input and output more
than 32. To accommodate circuits that require more
input and outputs, either multiple PLAs or PALs can
be used or a more sophisticated type of chip, called a
complex programmable logic device (CLPD).
CLPD is made up of multiple circuit blocks on a single
chip, with internal wiring to connect the circuit
blocks.

The structure of CLPD is shown on the next slide. It

includes four PAL-like blocks connected by
interconnection wires. Each block in turn is
connected to a sub-circuit I/O block, which is
attached to a number of input and output pins.
113
CPLD

block
I/O
PAL-like PAL-like
block

block block
I/O

Interconnection Wires

block
I/O
PAL-like PAL-like
block

block block
I/O

114
Section of CPLD blocks

PAL-like Block

PAL-like Block

D Q

D Q

115
CPLD
CPLD: a collection of PLDs to be connected to
each other through a programmable switch
matrix
 input/output blocks provide connections to IC pins
 each I/O pin is driven by a three-state buffer and
can be programmed to act as input or output
 switch matrix receives inputs from I/O block and
directs it to individual macrocells
 selected outputs from macrocells are sent to the
outputs as needed
 each PLD typically contains from 8 to 16 macrocells
 the macrocells within each PLD are usually fully
connected. If a macrocell has unused product terms
they can be used by other nearby macrocells.

116
CPLD
CLPD uses quad flat pack (QFP) type of package.
QFP package has pins on all four sides and the pins
extend outward from the package with a downward-
curving shape. Moreover, QFP pins are much thinner
and hence, they support a larger number of pins
when compared to the PLCC packing.

Most CPLDs contain the same type of switch as in

PLDs. Here, a separate programming unit is not used
due to two main reasons. Firstly, CLPDs contain 200
+ pins on the package, and these pins are often
fragile and easily bent. Secondly, a socket would be
required to hold the chip. Sockets are usually quite
expensive and hence, add to the overall cost
incurred.
117
CPLD
CLPD usually support the ISP technique. A small
connector is included on the PCB and is connected to
a computer system. CLPD is programmed by
transferring the programming information from the
CAD tool to into the CLPD.

The circuitry on the CLPD that allows this type of

programming is called JTAG, Joint Test Action Group
port, and is standardized by the IEEE.

JTAG is a non-volatile type of programming i.e

programmed state is retained permanently (for
example, in case of power failure, CLPD retains the
program).
118
CPLD

119
CPLD

1. Complexity of CPLD is between FPGA and PLD.

2. CPLD featured in common PLD:-
i. Non-volatile configuration memory – does not need an external
configuration PROM.
ii. Routing constraints. Not for large and deeply layered logic.

3. CPLD featured in common FPGA:-

i. Large number of gates available.
ii. Can include complicated feedback path.
4. CPLD application:-
i. Address coding
ii. High performance control logic
iii. Complex finite state machines
120
Comparisons between CPLDs and FPGAs

121
Look up Table (LUT)
A k input LUT can implement any Boolean function of k variables. The
inputs are used as addresses that can retrieve the 2k by 1-bit memory that
stores the truth table of the Boolean function.
Since the size of the memory increases with the number of inputs, k, in
order to optimize this mapping and reduce the size of the memory there are
a variety of algorithms that map a Boolean network, from a given
equation, into a circuit of k-input LUT. These algorithms minimize either
the total number of LUTs or the number of levels of LUTs in the final
circuit. Minimizing the total number of LUTs reduces the CLB
requirements while minimizing the levels of LUTs improves the delay.

122
 x1 x2 f1
Logic blocks are often
0 0 1
Look up Table (LUT) 0 1 0
f1= x1 x2 + x1 x2
1 0 0
Function to be implemented 1 1 1

0/1 1
0/1 0
0/1 0
0/1 1

Two input LUT

Storage Cell contents in the LUT
Before programming After programming

123
Look up Table (LUT)
abc def ghl jk l m

def

ghi

x y 4 input y
x
LUT
5 input
z LUT
z

f1= (abc + def) (g + h + i) (jk +lm) This can be implemented by

Four 5 input LUT

124
FPGA with example

• What is an FPGA
Field Programmable Gate Array

• An FPGA uses Re-configurable Logic Blocks

- we set the config bits of this block to set its Boolean logic function

- the configuration is a Truth Table (or Look Up Table) of functionality

In1 config Out

Out 000 NOT(In1)
In2 001 NOT(In2)
010 OR
config 011 NOR
100 AND
101 NAND
110 XOR
111 XNOR
FPGA with example

• LUTs = Look Up Tables

- we can program the LUTs to be whatever type of gate is needed by the design
- there are a finite number of LUTs within a given FPGA (also called "resources")

• The LUTs are configured into an ARRAY on the

silicon
- Array of LUT's = Array of Gates = Gate Array
In1
In2
Out
In1
In2
Out
In1
In2
Out

config config config

In1 In1 In1

Out Out Out
In2 In2 In2

config config config

In1 In1 In1

Out Out Out
In2 In2 In2

config config config

Programmable Logic

• Programmable Interconnect
- there are programmable interconnect switches that connect the LUTs

LUT X LUT X LUT

X X X X X

LUT X LUT X LUT

X X X X X

LUT X LUT X LUT

Programmable Logic

• Configuration
- We start with a Gate Level Schematic of our design (from synthesis)
- The FPGA LUTs are configured to implement Gates

LUT X LUT X LUT

X X X X X

LUT X LUT X LUT

X X X X X

LUT X LUT X LUT

Programmable Logic

• Configuration
- The interconnect switches are then programmed to implement the net connections

A INV X AND X LUT

B X X X X X Out

C INV X OR X LUT

X X X X X

LUT X LUT X LUT

Programmable Logic

• Configuration
- The LUT and Interconnect configuration is volative (i.e., it goes away when power is
removed)

- Since the programming is done by the user after fabrication, we call it "Field
Programmable" A INV X AND X LUT

B X X X X X Out

C INV X OR X LUT

X X X X X

LUT X LUT X LUT

- We now understand where Field Programmable Gate Array

Programmable Logic

• Adding More Functionality

- FPGA manufacturer's quickly learned that Flip-Flops would be useful

- They put a DFF next to a 4-Input LUT to form a "Configurable Logic Block" (CLB)

CLB X CLB

X X X

CLB X CLB
FPGA CLB with Look Up Table

FPGAs contain one basic "logic-cell"

duplicated thousands of times
Logic-cell: Small Look-Up Table
(LUT), D flip-flop and 2-to-1 MUX (to
bypass the flip flop if needed)
 Each logic-cell can be connected with
other logic-cell through interconnect
resources
 Complex logic can be implemented
CLB
FPGA CLB with Look Up Table

Look up table
FF, registers, clock storage elements
MUX

FPGA architecture CLB

FPGA CLB with Look Up Table
 LUT contains memory cells to implement logic function
 Each cell holds ‘0’ or ‘1’
 Programmed with outputs of truth table
 Inputs select content of one of the cells as output
 CAD for FPGA

Configured FPGA

Figure : Design flow

for FPGA
135
Design flow for Xilinx FPGA

136