ARM Instruction
Set
Types of ARM Instructions
Data-processing instructions
Load and Store Instructions
Branching and Control Flow
Multiply Instructions
Comparison and Test Instructions
Conditional Execution
System Control Instructions
Condition Codes (Flags)
ARM instructions use condition flags to determine if an operation should be
executed. These flags are set by comparison instructions and other
operations:
N (Negative): Set if the result is negative.
Z (Zero): Set if the result is zero.
C (Carry): Set if there is a carry out in arithmetic operations.
V (Overflow): Set if there is an overflow in the result.
These flags are used in conditional execution.
For example, ADDNE will only execute if the "Not Equal" condition is true,
meaning the Zero flag (Z) is not set
Instruction Execution Cycles
ARM processors generally follow a pipeline approach to execute
instructions, with multiple stages like:
Fetch: Get the instruction from memory.
Decode: Interpret the instruction.
Execute: Perform the operation (e.g., arithmetic or memory
access).
Write-back: Update the registers or memory with the result
Overview of Data Processing
Instructions
In the ARM instruction set, data-processing instructions are
used to perform a variety of arithmetic, logical, and other
operations on data stored in registers. These instructions are one
of the core elements of ARM's functionality and enable
operations such as addition, subtraction, multiplication, logical
operations, and comparisons.
Data-processing instructions in ARM work primarily on the values
contained in the general-purpose registers (R0-R12), although
they can also manipulate the status flags (N, Z, C, V) that
represent certain conditions like negative, zero, carry, or
overflow.
These instructions are typically
used for:
•Arithmetic operations (e.g., addition,
subtraction)
•Logical operations (e.g., AND, OR, XOR)
•Comparison operations (e.g., CMP)
•Move and shifting operations (e.g., MOV, ROR)
For Example: ADD R0, R1, R2 ; R0 = R1 + R2
Categories of Data Processing
Instructions
ADD (Addition)
•Adds the values in two registers and stores the result in a destination
register.
•Syntax: ADD <Rd>, <Rn>, <Rm>
•Example: ADD R0, R1, R2 (R0 = R1 + R2)
SUB (Subtraction)
•Subtracts the value of one register from another.
•Syntax: SUB <Rd>, <Rn>, <Rm>
•Example: SUB R0, R1, R2 (R0 = R1 - R2)
Logical Operations
AND (Logical AND)
Performs a bitwise AND between two registers.
Syntax: AND <Rd>, <Rn>, <Rm>
Example: AND R0, R1, R2 (R0 = R1 & R2)
ORR (Logical OR)
Performs a bitwise OR between two registers.
Syntax: ORR <Rd>, <Rn>, <Rm>
Example: ORR R0, R1, R2 (R0 = R1 | R2)
EOR (Exclusive OR)
EOR (Exclusive OR)
Performs a bitwise exclusive OR (XOR) between two registers.
Syntax: EOR <Rd>, <Rn>, <Rm>
Example: EOR R0, R1, R2 (R0 = R1 ^ R2)
BIC (Bit Clear)
Clears bits in the first operand that are set in the second operand (bitwise AND followed by
negation).
Syntax: BIC <Rd>, <Rn>, <Rm>
Example: BIC R0, R1, R2 (R0 = R1 & ~R2)
Comparison Operations
CMP (Compare)
Subtracts the second operand from the first and updates the condition flags, but
does not store the result.
Syntax: CMP <Rn>, <Rm>
Example: CMP R1, R2 (Updates flags based on R1 - R2)
CMN (Compare Negative)
Adds the second operand to the first and updates the condition flags.
Syntax: CMN <Rn>, <Rm>
Example: CMN R1, R2 (Updates flags based on R1 + R2)
Move and shifting Instructions
Shift and Rotate Logical and arithmetic are the two shift types.
There are six mnemonics for the different shift types :
a) Logical Shift Left (LSL)
b) Arithmetic Shift Left (ASL)
c) Logical Shift Right (LSR)
d) Arithmetic Shift Right (ASR)
e) Rotate Right (ROR)
f) Rotate Right with Extend (RRX)
Logical Shift Left :
Shifts left by the specified amount. LSL means "logical shift left by
the specified number of bits." This instruction is executed in a single
clock cycle. Example : LSL # n
Here n is the number of bit positions by which the value is
shifted. Shifting left by n-bit on a signed or unsigned binary
number has the effect of multiplying it by 2n.
Logical Shift Right (LSR)
LSR by 0 to 32 places, fill the vacated bits at the most significant
end of the word with zeros. Logical shifts can be useful as efficient
ways of performing multiplication or division of unsigned integers by
powers of two. Shifting right by n-bit on an unsigned binary number
has the effect of dividing it by 2n .
Arithmetic Shift Left and Right
Arithmetic Shift Left (ASL) is same as logical shift left. Arithmetic Shift Right
(ASR) by 0 to 32 places, fill the vacated bits at the most significant end of the
word with zeros if the source operand was positive and with ones it is
negative.
Rotate Right (ROR)
Rotate right by 0 to 32 places. The last bit rotated out is available
in the carry flag. Rotate left instruction is not used in ARM
processor. Rotate left by "n" positions is the same as a rotate
right by (32 - n).
Rotate Right Extended (RRX) It is always rotate
by one bit only.
The vacated bit is filled with the old value of the C flag and the
operand is shifted one place to the right. This operation uses the
CSPR C flag as a 33rd bit.
