Computer Organization

&
Architecture
1

C H A P T E R O NE
D i g i t a l L o g i c a n d Di g i t a l S y s t e m

By Feyisa B. 04/23/2025
 Computer Organization, Computer Design, and
Computer Architecture
Computer Organization :
 is concerned with the way the hardware computer operate and the way they are
connected together to form the computer system.
 The various components are assumed to be in place and the task is to investigate the
organizational structure to verify that the computer parts operation as intended.

Computer Design:
 is concerned with the hardware design of the computer.
 Once the computer specification is formulated, it is the task of the designer to
develop hardware for the system.
 It is concerned with the determination of what hardware should be used and how the
parts should be connected.
 It is the aspect of computer hardware and sometimes referred to as computer
By Feyisa B.
implementation. 2 04/23/2025
Computer Architecture:
 is concerned with the structure and behavior of the computer
as seen by the user.
 It includes the information formats, the instruction set and
techniques for addressing memory.

By Feyisa B. 3 04/23/2025
 Digital Computers
 Digital computers use the binary number system, which
has two digits, 0 and 1
 A binary digit is called a bit.
 Bits are grouped together as bytes and words to form
some type of representation within the computer.
 A sequence of instructions for the computer is known as
program.

By Feyisa B. 4 04/23/2025
 Figure of Block diagram of a digital computer
By Feyisa B. 5 04/23/2025
 The hardware of the computer is usually divided into three
major parts.

The Central processing Unit (CPU): contains an arithmetic

and logic unit for manipulating data, a number of registers for
storing data, and control circuits for fetching and executing
instructions.
The memory of a computer; contains storage for instructions
and data, it is called a Random Access Memory (RAM) ,the CPU
can access any location in memory at random and retrieve the
binary information within a fixed interval of time.

By Feyisa B. 6 04/23/2025
The input and output processor: contains electronic
circuit for communication and controlling the transfer of
information between the computer and the outside
world.
The input and output device: connected to the
computer include keyboards, printers, terminals,
magnetic disk drives and other communication devices.

By Feyisa B. 7 04/23/2025
 Logic Gates
Gates are the fundamental building block of all digital logic circuits.
Logical functions are implemented by the interconnection of gates.
Binary information is represented in digital computers using electrical
signals.
These signals can be represented by voltage to specify one of two
possible states.
The manipulation of binary information in a computer is done using logic
circuits called gates.
Examples: AND, OR, NOT, Buffer, NAND, NOR, X-OR, X-NOR
Each gate is defined in three ways: graphic symbol, algebraic
notation/function, and truth table

By Feyisa B. 8 04/23/2025
 Fig 1.2
A. AND Gate

The truth table of

AND gate

B. OR Gate
A
X=A+B
B

The truth table of OR

gate

By Feyisa B. 9 04/23/2025
C. Inverter

X = A’

D. Buffer

X=A

E. NAND

By Feyisa B. 10 04/23/2025
F. NOR
A

G. Exclusive-OR
(XOR)
x = A⊕ B
A or
x=A’B+AB’
B

H. Exclusive-NOR

X = (A⊕ B)’

By Feyisa B. 11 04/23/2025
Boolean Algebra
Boolean algebra is an algebra that deals with binary variables and logic
operations.
Variables are designated by letters such as A, B, x, and y.
A Boolean function can be expressed algebraically with binary variables, the
logic operation symbols, parentheses, and equal sign, and it can represent by:
truth table, logic diagram & algebraic expression
The result of a Boolean function is either 0 or 1.
Example: Consider the following Boolean function: F = xy + z‘
The function F is equal to 1 if either both x and y are 1 or z' is 1; F is equal to
0 otherwise.
NB: z' = 1 is equivalent to saying z = 0 since z' is the complement of z.

By Feyisa B. 12 04/23/2025
Basic Identities of Boolean algebra

(1) x+0=x (2) x*0=0

(3) x+1=1 (4) x*1=x

(5) x + x=x (6) x * x = x

(7) x + x' = 1 (8) x * x' = 0
(9) x + y=y+x (10) xy = yx
(11) x + (y + z) = (x + y) + z (12) x(yz) =
(xy)z
(13) x(y + z) = xy + xz)
(14) (x + y)' = x'y' (15) (xy)' = x' + y‘
(16) (x')' = x
De-Morgan’s Theorem
This theorem is very important in dealing with NOR and NAND gates. It
states that a NOR gate that performs the (x+y)’ function is equivalent to the
function x’y’. Similarly a NAND function can be expressed by either (xy)’ or
(x’+y’). For this reason the NOR and NAND gates have two distinct graphic
symbols.
By Feyisa B. 13 04/23/2025
 OR invert AND
invert
 The invert AND symbol for the NOR gate follows from the De-Morgan’s
thermo and from the convention that small circles denote complementation.
 Similarly the NAND gates have two distinct symbols as
shown below.
Invert OR
x
Y
z

AND-invert
x
y
z

By Feyisa B. 14 04/23/2025
 Complement of a
function
The complement of a function F when expressed in a truth table is obtained
by interchanging 1’s and 0’s in the values of F in the truth table.
When the function is expressed in algebraic form the complement of the
function can be derived by means of De-Morgan’s Theorem.
The general form of DeMorgan’s theorem can be expressed as follows:
(x1+x2+x3+….Xn) = x1’x2’x3’…xn’
(x1x2x3…xn)’ =x1’+x2’+x3’+…+xn’
By changing all OR operation to AND operation and all OR operations and
then complementing each individual letter variable we can derive a simple
procedure for obtaining the complement of an algebraic expression.
Eg. F = AB+C’D’+B’D F’=(A’+B’)(C+D)(B+D’)
NB: The complement expression is obtained by interchanging AND and OR
operations and complementing each individual.
By Feyisa B. 15 04/23/2025
Map Simplification
In addition to using Boolean algebra to simplify a Boolean
function, we use map simplification techniques/methods.
The map method is known as the Karnaugh map or K-map.
Each combination of the variables in a truth table is called a
minterm.
There are 2n minterms for a function of n variables.
The Boolean algebra can simplify by those two methods:
1. Sum-of- Products simplifications (SOP)
2. Product-of-sum simplifications (POS)

By Feyisa B. 16 04/23/2025
Variable Maps

The following are maps for two-, three-, and four-variable function:

By Feyisa B. 17 04/23/2025
The variable names are listed across both the sides of the diagonal line
into the corner of the map.
The 0’s and the 1’s marked along each row and each column designate
the value of the variables.
Each variable under the brackets contain half of the squares in the map
where that variable appears unprimed.
The minterm represent by a square is determined from the binary
assignment of the variable along the left top edges in the map.
Here the min term 5 the three variable maps are 101 of the second
column.
This minterm represents a value for the binary variables A, B and C with
A and C being unprimed and B being primed.
By Feyisa B. 18 04/23/2025
Sum-of-Products Simplification (SOP)
Minimization of SOP Boolean function using K-map
Follow the below procedure to minimize the SOP Expression.
1.Select the size of the K-map, based on the number of variables
present in the Boolean function.
2.Plot the K-map.
3.Check the K-map for isolated 1s, which are not adjacent to any
other 1s and encircle those isolated 1s.
4.Check the K-map for pair of 1s, which are adjacent to only one
other 1s and group it.
5.Check the K-map for quads and octets and group them, even if
contain any 1s, that have been already encircled.
6.Form the expression from the groups that have been encircled by
summing them.
Ex1 Let us minimize the expression F = AB’C + A’B’C + A’BC + AB’C’ + A’B’C’
or F(A,B,C) = Σm (0,1,3,4,5)
By Feyisa B. 19 04/23/2025
Solution:
Step 1: The given function has three variables and hence 2 3 = 8 cells K-
map is necessary to minimize the expression.
Step 2: Plotting of k-map.

Step 3: Group the pair of 1s in the K-map.

By Feyisa B. 20 04/23/2025
Step 4: Group the Quad of 1s in the K-map.

Step 5: There is no octet group and No isolated 1s are there in the K-

map.
Hence, from the K-map, the simplified output expression is F = A’C +
B’

Ex2. Let us minimize the Boolean expression F = ABC’D + ABC’D’ +

ABCD + A’BCD + ABCD’ + A’BCD’. Or F(A,B,C, D) = Σm
(6,7,12,13,14,15,)

F = AB + BC.
By Feyisa B. 21 04/23/2025
Ex3. Simplify the Boolean expression
F(A, B, C, D) = ∑ m (0, 1, 2, 3, 4, 7, 8, 9, 10, 11, 12, 14)

Plotting of k-map Group the pair, Quad and octet of 1s

in the K-map

Hence, from the K-map, the simplified output expression is

F= B’ + C’D’ + AD’ + A’CD

By Feyisa B. 22 04/23/2025
Minimization of POS Boolean function using K-map
Follow the below procedure to minimize the POS expression
1. Select the size of the K-map, based on the number of variables
present in the Boolean function.
2. Plot the K-map by placing 0s for the given Maxterms and place
1s for the remaining cells.
3. Check the K-map for isolated 0s, which are not adjacent to any
other 0s and encircle those isolated 0s.
4. Check the K-map for pair of 0s which are adjacent to only one
other 0s and group it.
5. Check the K-map for quads and octets and group them, even if
contain any 0s, that have been already encircled.
6. Form the expression from the groups that have been encircled by
summing them.
Ex1. Let us minimize the Boolean function
F = (A’+B’+C+D)(A+B’+C+D)(A+B+C+D’)(A+B+C’+D’)(A’+B+C+D’)
(A+B+C’+D).
By Feyisa B. 23 04/23/2025
Step 1: The given function has four variables and hence 2 4 = 16 cells K-map is
necessary to minimize the expression.
Step 2: Plotting of k-map Step 3: Group the pair of 0s in the K-
map

Step 4: There is no Quad and octet group of 0s.

Hence, from the K-map, the simplified output expression is F = (B’+C+D)
(B+C+D’) (A+B+C’)

By Feyisa B. 24 04/23/2025
Ex2. Simplify the Boolean function F(A, B, C, D) = Π M (2, 3, 8, 9, 11, 13,
15).
Solution:
Step 1: The given function has four variables and hence 2 4 = 16 cells K-
map is necessary to minimize the expression.
Step 2: Plotting of k-map.

Step 3: No isolated 0s are there in the K-map.

Step 4: Group the pair and quad of 0s in the K-map. There is no octet
group of 0s here

F= (A’+B+C)
(A’+D’) (A+B+C’)

By Feyisa B. 25 04/23/2025
Don’t care conditions in K-map
 In logic circuit design, there may be a situation, where
certain input and output conditions can never occur.
 In that case, the output can be either 0 or 1, that is, the
output cannot be defined for such inputs and so they are
indicated as ‘x’, which represents don’t care output.
Ex1. Simplify the Boolean function with don’t care conditions
F(A, B, C, D) = ∑ m (1, 3, 7, 11, 15) + d (0, 2, 5).

The K-map, the simplified output expression is F = A’B’ + CD

By Feyisa B. 26 04/23/2025
By Feyisa B. 27 04/23/2025
By Feyisa B. 28 04/23/2025
A. Combinational Circuits
A combinational circuit is a connected arrangement of logic gates with a set of
inputs and outputs.
At any given time, the binary values of the outputs are a function of the binary
values of the inputs.
The design of a combinational circuit starts from a verbal outline of the
problem and ends in a logic circuit diagram.
 The procedure involves the following steps:
o The problem is stated.
o The input and output variables are assigned letter symbols.
o The truth table that defines the relationship between inputs and
outputs is derived.
o The logic diagram is drawn
By Feyisa B. 29 04/23/2025
Half-Adder
The most basic digital arithmetic circuit.
Performs the addition of two binary digits.
The input variables of a half-adder are called the augends and the addend.
The output variables of a half-adder are called the sum and the carry.

half adder
S = x’y+xy’=x ⊕ y
C=xy

By Feyisa B. 30 04/23/2025
Full-Adder
A full-adder performs the addition of three binary digits.
Two half-adders can be combined to for a full-adder.
Full adder has three inputs and two outputs
The full adder circuit contains two half adders and an OR gate.

Full-adder
By Feyisa B. 31 04/23/2025
 B. Sequential Circuits
In Sequential Circuits the current output of a sequential circuit depends on the
current input and the current state of that circuit.

By Feyisa B. 32 04/23/2025
Flip Flops
Is the simplest form of sequential circuit
There are a variety of flip flops,
all of which share two properties:
1. The flip-flop is a bi-stable device. It exists in one of two states and, in
the absence of input, remains in that state.
2. The flip-flop has two outputs, which are always the complements of
each other. These are generally labeled Q and Q’ (Q complement).
A Flip-flop is a binary cell capable of storing one bit of information.
It has two outputs, one for the normal value and one for the complement value
of the bit stored in it.
Flip-flops are storage elements utilized in synchronous sequential circuits.

By Feyisa B. 33 04/23/2025
 Synchronous sequential circuits employ signals that effect storage elements only at
discrete instances of time.
A timing device called a clock pulse generator that produces a periodic train of
clock pulses achieves synchronization.
Values maintained in the storage elements can only change when the clock pulses.
Hence, a flip-flop maintains a binary state until directed by a clock pulse to switch
states.
The difference in the types of flip flops is in the number of inputs and the manner
in which the inputs affect the binary state.
Flip-flops can be described by a characteristic table which permutates all possible
inputs (just like a truth table).
The characteristic table of a flip-flop describes all possible outputs (called the next
state) at time Q(t+1) over all possible inputs and the present state at time Q(t).
By Feyisa B. 34 04/23/2025
 The most common types of flip flops are:
 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop

SR Flip-Flop or S-R Latch

Has 3 Inputs: Graphic Truth table

symbol
 S (for set)
 R (for reset)
 C(for Clock)
Has 2 Outputs:
 Q
 Q'B.
By Feyisa 35 04/23/2025
The operation of the SR flip-flop is as follow.
If there is no signal at the clock input C, the output of the circuit cannot change
irrespective of the values at inputs S and R.
Only when the clock signals changes from 0 to 1 can the output be affected
according to the values in inputs S and R
If S =1 and R = 0 when C changes when C changes from 0 to 1 output Q is set
to 1. If S = 0 and R =1 when C changes from 0 to 1.
If both S and R are 0 during the clock transition, output does not change.
When both S and R are equal to 1, the output is unpredictable and may go to
either 0 or 1, depending on internal timing that occur within the circuit

By Feyisa B. 36 04/23/2025
D Flip-Flop

Inputs:
Graphics Symbol
D (for data)
C (for clock)
Outputs:
Q
Q'
JK Flip-Flop
Inputs: Graphics
Symbol
J
K
C
Outputs:
Q Q'

By Feyisa B. 37 04/23/2025
T Flip-Flop

Inputs:
T (for toggle)
C (for clock)
Outputs:
Q
Q'

Most flip-flops are edge-triggered flip-flops, which means that the transition
occurs at a specific level of the clock pulse.
A positive-edge transition occurs on the rising edge of the clock signal.
A negative-edge transition occurs on the falling edge of the clock signal.
Another type of flip-flop is called a master-slave flip-flop that is basically two
flip-flops in series.

By Feyisa B. 38 04/23/2025
Flip-flops can also include special input terminals for setting or
clearing the flip-flop asynchronously.
These inputs are usually called preset and clear and are useful for
initialing the flip-flops before clocked operations are initiated

Reading Assignment
1. What is Counters?
2. What is Programmable Logic Array (PLA)?
3. What is Physical considerations (gate delays, fan-in, fan-out)?

By Feyisa B. 39 04/23/2025
Registers

Is one of the essential elements of the CPU:

is a digital circuit used within the CPU to store one or more bits
of data.
Two basic types of registers are commonly used:
1. parallel registers and
2. shift registers.
1. Parallel Registers:
 parallel register consists of a set of 1-bit memories that can
be read or written simultaneously.
 It is used to store data.
By Feyisa B. 40 04/23/2025
 NB: Figure below illustrates the operation of a parallel register using D flip-flops.

8 bit parallel register

By Feyisa B. 41 04/23/2025
2. Shift Register:
A shift register accepts and/or transfers information serially.
for example,
Figure below which shows a 5-bit shift register constructed from clocked D flip-
flops.
Data are input only to the leftmost flip-flop. With each clock pulse, data are
shifted to the right one position, and the rightmost bit is transferred out.
Shift registers can be used to interface to serial I/O devices.
In addition, they can be used within the ALU to perform logical shift and rotate
functions.

5 bit shift register

By Feyisa B. 42 04/23/2025
 !
d!
En

By Feyisa B. 43 04/23/2025