D E PA RT M E N T O F E C E , V L S I S Y S T E M
FinFET
Technology
Presented By : Sairam K
(208224026)
1
Scaling of Transistors
As the devices got scaled down 32 nm or below (i.e around 2010), a host of
effects knocked the doors of design engineers like SCE, DIBL, Gate
Tunnelling leakage, Subthreshold Leakage and Vth shifts. So what was
the solution? 2
FinFET Technology
Around 2011, for the sub 32 nm
technologies, the FinFET technology was
adopted,
FinFET is abbreviated as
- Fin Field Effect Transistor; which
comes from its visual shape, similar to
that of a fish’s dorsal fin.
FinFET comes under the category of
Multi-Gate Field Effect Transistor
(MuGFET) which has better stability,
Higher Ion/Ioff, decreased Short Channel
Effects (SCE). 3
FinFET Vs MOSFET Structure
While the channel of a planar device is horizontal, the FinFET channel is a
thin vertical “fin” with the gate fully wrapped-around
the channel formed between the source and the drain.
The current flows parallel to the die plane whereas the conducting channel is
formed around the edges of the fin. With this structure, the gate is able to fully
deplete the channel so that it has much better electrostatic control over the 4
FinFET Fabrication
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FinFET Fabrication cntd…
While the fabrication of FinFETs is relatively straightforward and compatible with
the conventional planar device fabrication process, the fin shape control is a
challenge:
Certain Fabrication Advances:
Multi Patterning
Fin Shapes
6
FinFET Structure Classification
Based on Physical Structures
Based on Number of Terminals
Based on Dielectric Thickness
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FinFET Structure Classification
Based on Physical Structures
Bulk FinFET:
• Individual fins share a common substrate, leading to
their physical connection.
• Bulk FinFETs closely resemble the traditional planar
MOSFET structure, making the transition from planar
MOSFETs to Bulk FinFETs a relatively straightforward
process.
SOI FinFET:
• SOI FinFETs are designed with physically isolated fins
that do not come into direct contact.
• More complex isolation structure compared to Bulk
FinFETs
Bulk FinFETs and SOI FinFETs remains a topic of debate among engineers, hinging on
factors such as cost and performance considerations.
The decision regarding which type to adopt; depends on a complex interplay of these
variables and specific design requirements.
8
FinFET Structure Classification
Based on Number of Terminals
Short Gate FinFET (SG FinFET):
• It has three terminals.
• Two gates are shorted and physically connected to each
other
• Exhibits Higher Ion/Ioff value compared to its
counterpart.
Independent FinFET (IG FinFET):
• IG FinFET features four terminals.
• The gates are physically isolated by a dielectric
material
• IG FETs provide greater versatility in transistor control
by allowing the application of varying voltages and
signals to the gate terminal
• Better suited for power management applications.
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FinFET Structure Classification
Based on Dielectric Thickness
Double Gate FinFET (DG FinFET):
• In DG FinFET, a hard mask is employed atop the
transistor structure, ensuring that the effective channel
width is equal to two times the fin height. (also called
split transistor).
Tri-Gate FinFET (TRIG FinFET):
• Here in TRIG FinFET dielectric thickness is reduced, the
effective channel width in Tri-gate FinFETs becomes
equivalent to the DG FinFET’s channel width plus the
width.
• Consequently; total channel length: 2x fin height + fin-
width.
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FinFET Symbol and Circuit
NMOS PMOS
2 i/p NAND gate
Based on SG FinFET
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FinFET Materials Used
Materials used in FinFET Fabrication
Gate Dielectric Materials
Channel Materials
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FinFET Materials Used
Materials used in FinFET Fabrication
A variety of materials and techniques are being used for FinFET Fabrication.
Material used in FinFET Improvement achieved
FinFET based dual KK-structure Improved cutoff frequency (fT) and maximum
oscillation frequency (fmax)
InGaAs-on-Insulator FinFET Optimized for on/off current trade-off.
Expanded gate length and width (upto 20nm)
Double Gate based n-FinFET using (HfO2 + Au) At 22 nm and 20 nm technology
shows reduced leakage current and high
Ion/Ioff
SOI-FinFETs Features ultra-narrow fin widths (down to 5
nm) and tall fins (65 nm).
Selective Epitaxial Si Growth in FinFET Enhances fin structures and repairs the outer
surface of the fin
Atomic Layer Deposition (ALD) in FinFET Ensures uniform high-k material deposition in
FinFETs and Improvement in threshold voltage 13
FinFET Materials Used
Gate Dielectric Materials
The objective is to reduce leakage current and balance energy consumption. So we use High-k
dielectric for strong electrostatic control and High Ion/Ioff ratio.
Common Dielectric Materials used
Al2O3, SiO2, Si3N4, ZrO2, Y2O3, Ta2O5.
HfO2 - Demonstrates high drain current (Ion)
LaZrO2 -
• Cutting edge material with High dielectric constant, broad energy band-
gap.
• Superior performance in 14 nm FinFETs (ITRS standards).
• On-current ↑ by 2.7 times, off-current ↓ by 101 times. SS ↓ by 10%, DIBL ↓
by 76%.
TiO2 - Enhances Vth, mitigates SCEs
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FinFET Materials Used
Channel Material
Silicon (Si) in the channel yields the highest ION (5.03 × 10⁻⁶ A).
Gallium Arsenide (GaAs) offers the lowest subthreshold swing (SS) of 58 mV/dec.
Silicon Carbide (SiC₃C) provides the highest ION/IOFF ratio (1.90 × 10¹¹) and the lowest IOFF
(7.00 × 10⁻¹⁹ A).
For better DIBL (Drain-Induced Barrier Lowering) qualities and threshold voltage roll-off,
Gallium Nitride (GaN) and GaAs are recommended.
Other Potential Materials: Carbon Nanotubes (CNTs) and Graphene for further Ion/Ioff
improvement
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FinFET Challenges
Parasitic Capacitance
Corner Effects
Quantum Effects
Crystal Orientation for Fin-Surface
Threshold Voltage Adjustment
Doping Concentration
Integration Challenges
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FinFET Challenges
Parasitic Capacitance
FinFET devices will exhibit a higher incidence of parasitic capacitance
(compared to Planar MOSFETS). Why?
Due to increased overlap between the front and back gates
Mitigation:
• elevating the fin height while simultaneously reducing the fin pitch
Quantum Effects
Thick Fin Impact:
Weakened gate control over the fin’s sides and top.
Fin body behaves similarly to a bulk substrate, losing FinFET benefits.
Thin Fin Consequences:
Quantum effects reduce the density of electron/hole states at the band
edge.
Electrons/holes need more energy to occupy higher states, hindering 17
current conduction.
FinFET Challenges
Corner Effects
Reducing Fin-Width: Helps minimize SCE but leads to performance
trade-offs.
Performance Degradation: Arises due to higher parasitic
drain/source resistance, lowering drive current and trans-conductance.
Subthreshold Leakage: Higher concentration of subthreshold leakage
current at the corners of the fin due to the events said above is called
the “corner effect”
Heat Flow Restriction: Smaller fin width hampers heat dissipation,
causing higher device temperatures.
Solution: Implementing a more curved and rounded fin profile in
FinFET production helps mitigate these issues.
18
FinFET Challenges
Threshold Voltage Adjustment
Full Depletion: The FinFET channel becomes fully depleted, so
threshold voltage (VT) adjustment depends on the gate work
function (WF) of the metal electrode.
Moderate VT: Achieved using mid-gap metals like TiN.
Low VT: Requires additional cap layers, such as La₂O₃ for NMOS
and Al₂O₃ for PMOS, placed between the high-k dielectric and
metal electrode.
Layer Thickness: The thickness of these cap layers is crucial,
necessitating precise deposition using Atomic Layer Deposition
(ALD) to ensure a conformal gate stack around the fin.
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FinFET Challenges
Doping Concentration
To monitor leakage current and threshold voltage; light doping of channel is done.
But this leads to elevated series resistance in source and drain regions
Mitigation:
• Incorporate Epitaxial growth within the fabrication process.
Crystal Orientation for Fin-Surface
Surface orientation and current flow direction play crucial roles in determining the
mobility of electrons and holes.
For electrons: (100) orientation for the highest surface mobility while (110)
orientation for the lowest mobility.
For Holes: (110) orientation show the highest mobility and the least in (100)
orientation.
Mitigation:
These both are now contradicting with each other. Hence a 111 orientation is
adopted to serve as a middle ground to obtain the benefits of both. 20
Sensing Applications of FinFET
Ion Sensing:
Ion-sensitive floating gate FinFET (ISFGFinFET)
using a 3D nano-seaweed structure that can
detect multiple ions simultaneously (e.g. H+,
Na+ ions..etc) with High Sensitivity and
Precision to a mV per pH, making it a viable
option for Biomedical Applications.
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Sensing Applications of FinFET
Junctionless FinFET Biosensor- Sub Biomolecular Sensing using
20nm GaAs: NCFinFET:
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Future Prospects
Beyond Silicon:
Research is ongoing to integrate FinFETs with alternative channel materials, like silicon-
germanium (SiGe) and III-V compounds, to enhance mobility.
3D Integration:
- 3D stacking of FinFET devices is gaining interest for higher density and performance.
Industry Adoption:
- Samsung and TSMC are transitioning towards 3nm nodes using GAAFET for High Performance
Computing Applications; while AMD and Qualcomm are transitioning towards 4nm nodes for
their processor architectures focused on AI, Mobile Computing and Gaming.
Transition to Gate-All-Around (GAA) FETs:
- GAA transistors, such as nanosheet and nanowire FETs, are emerging as successors to
FinFETs to provide even better electrostatic control.
- GAA device architecture, Short Channel Effects are reduced compared with FinFETs at the
same technology node.
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Future Prospects
GAAFET and MBCFET:
- Among the gate-all-around architectures investigated by the semiconductor
industry, nanowires offer the best electrostatic control, while wider
nanosheets provide higher “on” current and enhanced electrostatic
control compared with FinFETs .
- Gate-all-around (GAA) nanosheet field-effect transistors (FETs) have been widely
adopted by the industry to continue logic scaling beyond the 5 nm technology
node, surpassing FinFETs.
- Eg: MBCFET (Multi Bridge Channel) - by Samsung in their 3nm node (as shown
below)
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Conclusion and References
Conclusion:
- Thus from Scaling to FinFET, then to FinFET fabrication followed by its challenges
were discussed.
- The Integration Challenge for FinFET is left as an exercise for the readers in the
reference.
- One sensing application based on Ion Sensing were discussed.
- Followed by the Future Prospects of FinFET were discussed and closed.
References:
- https://www.mdpi.com/2072-666X/15/10/1187
- https://www.synopsys.com/glossary/what-is-a-finfet.html
- samsung.com
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Thank You for your Patience!
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