Chapter 3
Top Level View of Computer
Function and Interconnection
WILLIAM STALLINGS
COMPUTER ORGANIZATION
AND ARCHITECTURE
INSTRUCTION FETCH AND EXECUTE
Execution cycle for a particular instruction
may involve more than one reference to
memory.
Also, an instruction may specify I/O
operation, instead of memory references.
With these considerations, fig 3.6 provides a
detailed look at the basic instruction cycle of
fig 3.3.
INSTRUCTION CYCLE STATE DIAGRAM
States in the upper part of the figure involve an exchange between the
processor and memory/IO module.
States in the lower part of the fig involve only internal processor
operations.
INTERRUPTS
Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing. Common classes of
interrupts(table 3.1)
Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer- allows
OS to perform certain functions on a regular
basis.
I/O
Generated by an I/O controller
Hardware failure
Interrupts are provided primarily as a way
to improve processing efficiency.
Example: Most external devices are much
slower than the processor. Suppose that
the processor is transferring data to a
printer. After each write operation, the
processor must pause and remain idle until
the printer catches up. The length of this
pause may be on the order of many
hundreds or even thousands of instruction
cycle that do not involve memory.
PROGRAM FLOW CONTROL
FIG 3.7 EXPLANATION
Code segments 1,2,3 refer to sequences of instructions
that do not involve I/O.
The WRITE call are to an I/O program.
The I/O program consists of instructions, labeled4, to
prepare for the actual I/O operation. This may include
copying the data to be output into a special buffer and
preparing the parameters for a device command.
I/O command is the actual command. If interrupt is not
generated then user program will wait for the I/O device
to perform the function.
A sequence of instructions labeled 5, to complete the
operation. This may include setting flag indicating
success or failure of the operation.
With interrupts, the processor can be engaged in executing other
instructions while an I/O operation is in progress.
Consider the flow of control in fig 3.7b.
When user program reaches to WRITE call the I/O program is
invoked and only the preparation code and I/O Command is
executed. The control returns back to the user program,
meanwhile the external device is busy accepting data from
computer memory and printing it.
When external device is ready to be serviced i.e. to accept data
from the processor, the I/O module for that external device
sends an interrupt signal to the processor. The processor respond
by suspending the current program and branching off to a
program to service that particular device, known as interrupt
handler and resuming to the original execution after the device
is serviced.
INTERRUPT CYCLE
Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler
routine
Process interrupt
Restore context and continue interrupted
program
TRANSFER OF CONTROL VIA
INTERRUPTS
INSTRUCTION CYCLE WITH
INTERRUPTS
PROGRAM TIMING SHORT I/O WAIT
PROGRAM TIMING LONG I/O WAIT
INSTRUCTION CYCLE (WITH
INTERRUPTS) - STATE DIAGRAM
MULTIPLE INTERRUPTS
Multiple interrupts can occur.
For example: a program may be receiving
data from a communication line and printing
results.
The printer will generate an interrupt every
time it completes a print operation.
The communication line controller will generate
an interrupt every time a unit of data arrives.
It is possible for a communication interrupt to
occur while a printer interrupt is being
processed.
DEALING WITH MULTIPLE INTERRUPTS
Two approaches can be taken to deal with multiple interrupts.
Disable interrupts
will ignore further interrupts while processing one interrupt
Interrupts remain pending and are checked after first interrupt has
been processed
Interrupts handled in sequence as they occur
Drawback
It does not take into account relative priority or time-critical needs.
Example: when input arrives from communication line, it may need to
be absorbed rapidly to make room for more input. If the first batch
of input has not been processed before the second batch arrives, data
may be lost.
Define priorities
Low priority interrupts can be interrupted by
higher priority interrupts
When higher priority interrupt has been
processed, processor returns to previous
interrupt
MULTIPLE INTERRUPTS - SEQUENTIAL
MULTIPLE INTERRUPTS – NESTED
TIME SEQUENCE OF MULTIPLE
INTERRUPTS
INTERCONNECTION STRUCTURES
A computer consists of a set of components
or modules of three basic types(processor,
memory, I/O)that communicate with each
other.
The collection of paths connecting the
various modules is called the
interconnection structure.
COMPUTER MODULES
MEMORY CONNECTION
Receives and sends data
Receives addresses (of locations)
Receives control signals
Read
Write
Timing
INPUT/OUTPUT CONNECTION(1)
Similar to memory from computer’s
viewpoint
Output
Receivedata from computer
Send data to peripheral
Input
Receivedata from peripheral
Send data to computer
INPUT/OUTPUT CONNECTION(2)
Receive control signals from computer
Send control signals to peripherals
Receive addresses from computer
e.g. port number to identify peripheral
Send interrupt signals (control)
CPU CONNECTION
Reads instruction and data
Writes out data (after processing)
Sends control signals to other units
Receives (& acts on) interrupts
THE PRECEDING LIST DEFINES THE DATA TO BE
EXCHANGED.
THE INTERCONNECTION STRUCTURE MUST SUPPORT
THE FOLLOWING TYPES OF TRANSFER.
Memory to processor: the processor reads
an instruction or unit of data from memory
Processor to memory: the processor
writes a unit of data to memory
I/O to processor: the processor reads data
from an I/O device via an I/O module.
Processor to I/O: the processor sends data
to the I/O device.
I/O to or from memory: an I/O module is
allowed to exchange data directly with
memory without going through processor,
using direct memory access.
