Braun Multiplier
Dr.E.Srinivas
Associate Professor
Dept. of E.C.E
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Introduction:
Braun Edward Louis First proposed the Braun multiplier in 1963.
i) It is a simple parallel multiplier that is commonly known as the Carry Save
Array Multiplier.
(ii) This multiplier is restricted to performing multiplication of two unsigned
numbers.
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Architecture of Braun multiplier:
An nxn-bit Braun multiplier requires n(n-1) adders and
n2 AND gates.
One efficient implementation of the multiplier is the regular layout of the adder
array.
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A 4×4 bit basic Braun multiplier 4
A: 4-Bit multiplicand
B: 4-Bit multiplier
P 8-bit product of X and Y
Schematic diagram of 4x4-bit Braun Multiplier Architecture 5
Speed Considerations:
• The delay of the braun multiplier is dependent on the delay of the full adder and
also on the final adder in the last row.
• In the multiplier array, a full adder with balanced carry and sum delays is desirable
• Because the sum and carry signals are both in the critical path.
tBraun = (n-1)tcarry-save + tAND+ (n-1)tRipple-Carry
Where
tcarry-save = time required to generate Carry-out(Cout) or Sum(Sout) at
the output after the inputs are supplied to a CSA.
tRipple-Carry = time taken for the Carry-out(Cout) or Sum(Sout) to be generated at the
output after the inputs are supplied to a RCA.
tAND =delay of an AND gate
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Advantages:
1. Minimum Complexity
2. Easily Scalable
3. Easily Pipelined
4. Regular shape, easy to place & Route
Disadvantages:
5. High Power Consumption
6. More Digital gates resulting in large chip area
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Applications :
1. It is arithmetic operation for DSP applications
2. Such as ‘Filtering’ and for Fourier transform
3. To achieve high execution , speed parallel array multipliers are widely used.
4. These multipliers tend to consume most of power in DSP computations.
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Baugh-Wooley Multiplier:
The Baugh-Wooley multiplier is an enhanced version of the Braun multiplier.
It is designed to cater to multiplication of both signed and un-signed
operands, which are represented in the 2’s complement number systems.
The partial products are adjusted so that the negative signs are moved to the last steps,
Which in turn maximize the regularity of multiplication array.
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Statement :
Baugh-Wooley multiplication is one amongst the costeffective ways to handle the sign bits.
This method has been developed so as to style regular multipliers, suited to 2's
compliment numbers Baugh-Wooley algorithm for the unsigned binary multiplication
is based on the concept.
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Signed multiplicands must first be converted in to their 2’s complement representation
before multiplication.
A 2’s complement generator is shown in fig.4.6.
It is basically a combinational circuit that will either pass the input
unchanged or convert it into the 2’s complement form.
When the control line Comp-Sig(Complementary Signal) goes high, the XOR gates
invert the input bits and a 1 gets added to the result.
The generated result is the 2’s complement of the input bits.
On the contrary, when the Comp-Sig goes low, the multiplicand inputs do
not get inverted and a 0 gets added to them.
Once the signed multiplicands get processed, the most significant bit (MSB) of the
Result would then indicate the sign of the result( 1 for negative, 0 for positive). 14
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Performance consideration:
The area and power consumption of a number of multiplier structures
vary with the number of bit operands and the layout strategies.
Increasing regularity and locality at the silicon level reduces the
power consumption in a standard-cell based design flow.
Since the Baugh-Wooley multiplier is an evolvement of the Braun multiplier,
Its performance can also be improved by using the earlier-mentioned optimized
Interconnections.
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Disadvantages:
1. hardware complexity,
2. need large routing area
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Booth Multiplier :
Area-efficient and fast multipliers are the essential blocks for high-performance computing.
Therefore, multipliers should be small enough so that a larger number of them may be
integrated on a single chip.
Conventional array multipliers, like the Braun multiplier and the Baugh-Wooley multiplier,
Achieve comparatively good performance ,but they require large areas of silicon, unlike the
add-shift algorithms, which require less hardware and exhibit poorer performance.
The Booth multiplier makes use of the booth encoding algorithm in order to reduce the
number of partial products by considering two bits of the multiplier at a time,
thereby achieving a speed advantages over other multiplier architectures. This algorithm is
valid for both signed and unsigned operands 18
Booth’s Algorithms:
In 1951, A.D Booth Proposed the Booth algorithms ( also known as the radix-2
algorithm) for multiplication that accepts numbers in 2’s complement form,
based on radix-2 computation.
It can Handle signed binary multiplication by using 2’s complement representation.
This increases the complexity of how the signs of the operands get stored in auxiliary
circuits.
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Table 4.3 Recoding in Booth Algorithm
Xi Xi-1 Operation on multiplicand A. yi
0 0 One bit shift to the right only. 0
0 1 Add A to the existing sum of partial products +1
and then shift the result one bit to the right
1 0 Subtract A from the current sum of partial products -1
and then shift the result one bit to the right
1 1 One bit shift to the right only. 0
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Thank
you
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