Chapter Two.

The 8086 Microprocessor Architecture

1
Outline of the chapter

 Features of 8086
 Architecture of 8086
 Register Organization
 Bus Operation
 Memory Segmentation
Features of 8086
 The 8086 is a 16-bit microprocessor.
 The term "16-bit" means that its ALU, internal registers and most
of its instructions are designed to work with16-bit binary words.
 The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.
 The 8086 has a 20-bit address bus, so it can directly access or
1,048,576 (1Mb) memory locations.
 Each of the 1,048,576 memory locations is byte wide.
 Therefore, a 16 bit words are stored in two consecutive memory
locations.
 The 8086 provides fourteen 16-bit registers.
Features of 8086

 The 8086 has multiplexed address and data bus which

reduces the number of pins needed, but does slow down the
transfer of data (drawback).
 It performs the arithmetic and logic operations on bit, byte,
word and decimal numbers including multiply and divide.
Features of 8086
 The Intel 8086 is designed to operate in two modes, namely
a. The minimum mode and
b. The maximum mode.
 Min.= Control signals are issues by CPU,
 Max.= Control signals are issued by external bus controller (8288).

 The Intel 8086 supports multiprogramming.

In multiprogramming, the code for two or more processes is in memory at
the same time and is executed in a time-multiplexed fashion.
 Intel 8086 has 6 bytes instruction cache or queue.
 The 8086 provides powerful instruction set with different
addressing modes such as:-
 Register, immediate, direct, indirect through an index or base,
indirect through the sum of a base and an index register, relative and
implied.
Block Diagram Architecture
 The simplified block diagram of the 80x86 processor model is organized as two separate
processors :
 Bus Interface Unit (BIU)
 Execution Unit (EU).
Block Diagram Architecture
 These two functional units(BIU & EU) can work simultaneously to
increase system speed and hence the No. of IPS.
 BIU:
 Is the 8086’s interface to the outside world and provides a full 16-bit
bi-directional data bus and 20-bit address bus.
 Sends address of the memory or I/O,
 Fetches instruction from memory,
 Reads/writes data from/into port/memory,
 Supports instruction queuing and
 To implement these functions; the BIU contains:-
• The instruction queue, segment registers, instruction pointer,
address summer and bus control logic.
Architecture of 8086
 INSTRUCTION QUEUE:
• The main linkage between the two functional blocks is the instruction
queue.
• To speed up program execution, BIU fetches six instruction bytes ahead of time
from the memory and holds for the EU in a group of registers called Queue.
• Queue makes possible to fetch next instruction when current instruction is in
execution.
• In case of JUMP and CALL instructions, instruction already fetched in queue are
of no use.
• Fetching the next instruction while the current instruction executes is called
pipelining.
Architecture of 8086
 EXECUTION UNIT (EU):-
• The EU of 8086:-
 Tells the BIU from where to fetch instructions or data,
 Executes instructions.
• It contains:
 Control circuitry
 Instruction decoder
 ALU
 Register Organization
 Flag register
 General purpose register
 Pointers and Index registers
Architecture of 8086
 CONTROL CIRCUITRY, INSTRUCTION
DECODER, ALU:
• The control circuitry in the EU directs the
internal operations.
• A decoder in the EU translates the
instructions fetched from memory into
a ,series of actions which the EU performs.
• ALU is 16-bit. It can add, subtract, AND, OR,
XOR increment, decrements, complement and
shift binary numbers.
REGISTER ORGANIZATION
The 8086 has a powerful set of registers.
It includes:-
 General purpose registers,
 Segment registers,
 Pointers and index registers, and
 Flag register.
 The fig 2.4 shows the register
organization of 8086.
 It is also know as programmer’s model
of 8086.
 The registers shown in programmer’s
model are accessible to programmer.
 All registers of 8086 are 16-bit registers.
Register Organization
GENERAL PURPOSE REGISTERS:
 The 8086 has four 16-bit general purpose
registers labeled AX, BX, CX and DX.
 They are used for holding data, variables and
intermediate results temporarily.
 They can also be used as a counters or used for
storing offset address for some particular
addressing modes.
 AX is used as 16-bit accumulator whereas AL is
used as 8-bit accumulator.
 BX is used as offset storage for generating
physical addresses in case of certain addressing
modes.
 CX is used as a default counter in case of string
and loop instructions.
 Register Organization
SEGMENT REGISTERS:
 The physical address of the 8086 is 20-bit wide to access 1
Mbyte memory locations.
 However, its registers and memory locations which contain
logical addresses are just 16-bits wide.
 8086 uses memory segmentation. It treats the 1 Mbyte of
memory as divided into segments, with a maximum size of a
segment as 64 Kbytes.
 The 8086 allows only four active segments at a time, as
shown in fig 2.5 and 16-bit segment registers are used for the
selection.
 These four segment registers are:
 Code segment (CS) register,
 The data segment (DS) register,
 The stack segment (SS) register, and
 The extra segment (ES) register.
Segment registers
• Segmentation is the process in which the main memory of the computer is
divided into different segments and each segment has its own base
address.
• It is basically used to enhance the speed of execution of the computer
system, so that processor is able to fetch and execute the data from the
memory easily and fast.
• Segment registers are basically memory pointers located inside the CPU.
• Segment registers point to a place in memory where one of the following
things begin:
• Data storage
• Code execution.
Cont…
• Code segment register (CS): is used for addressing memory location in the code
segment of the memory, where the executable program is stored.
• holds the upper 16-bits of the starting address of the code segment.
• Data segment register (DS): points to the data segment of the memory where the
data is stored.
• Extra Segment Register (ES): also refers to a segment in the memory which is
another data segment in the memory.
• ES and DS registers are used to hold the upper 16-bits of the starting address of the two memory segments
which are used for data.
• Stack Segment Register (SS): is used for addressing stack segment of the memory.
The stack segment is that segment of memory which is used to store stack data.
• holds the upper 16-bits of the starting address of the program stack segment.
Flag registers
• The FLAGS register is the status register that contains the current state
of a CPU.
• The size and meanings of the flag bits are architecture dependent.
• It usually reflects the result of arithmetic operations as well as
information about restrictions placed on the CPU operation at the
current time.
• Some of those restrictions may include preventing some interrupts
from triggering, prohibition of execution of a class of "privileged"
instructions. Additional status flags may bypass memory mapping and
define what action the CPU should take on arithmetic overflow.
 Register Organization
FLAG REGISTER
 A flag is a flip-flop which indicates some condition produced by the
execution of an instruction or controls certain operations of the EU.
 The flag register contains nine active flags as shown in the figure.
 Six of them are used to indicate some condition produced by
instruction.
FLAG REGISTER
 CF: CARRY FLAG :-
 Is set if there is a carry out of the MSB or used as borrow flag for subtraction (it is set when borrow is
needed)
 PF: PARITY FLAG :-
 Is set if result of byte operation or lower byte of the word operation contain an even number of ones.
 AF: AUXILIARY FLAG:-
 Is set if there is an overflow out of bit 3 and is used for BCD operations. Not available for the
programmer.
 ZF: ZERO FLAG:-
 Is set if result of ALU is zero. And also if certain register content becomes zero following an
increment or decrement operation.
 SF: SIGN FLAG :-
 Is set if MSB of the result is 1.
 OF: OVERFLOW FLAG
 Is set if result is out of range.
 For addition this flag is set when there is a carry into the MSB and no carry out of the MSB or vice-
versa.
 For subtraction, it is set when the MSB needs a borrow and there is no borrow from the MSB, or vice
versa.
FLAG REGISTER
What is the value of CF,ZF,PF,AF
and OF for the following
• 1.

• 2.

• 3.
Flag Register
 The three remaining flags are used to control certain
operations of the processor.
 TF: Trap flag is used for single stepping through a program (for debugging).
 If TF is set a trap is executed after execution of each instruction, i.e.
interrupt service routine is executed which displays various registers and
memory variable contents.
 IF: Interrupt flag is used to allow/ prohibit the interruption of a program.
 If set, a certain type of interrupt can be recognized by the 8086; otherwise
these interrupts are ignored.
 DF: direction flag is used with string instruction.
 If DF = 0, the string is processed from its beginning with the first element
having the lowest address.
 Otherwise, the string is processed from the high address towards the low
address.
 Register Organization
POINTERS AND INDEX REGISTERS
• The registers in this group are all 16 bits wide and, unlike the data
registers, cannot be accessed as a low or high byte.
• These registers are used as memory pointers.
• Recall that all segment registers are 16-bit wide. But it is necessary
to generate 20-bit address (physical address) on the address bus.
• To get 20-bit physical address one or more pointer or index
registers are associated with each segment register.
• The pointer registers IP, and BP & SP are associated with code,
Data and stack segments, respectively.
• The index registers DI & SI are used as a general purpose
registers as well as for offset storage in some addressing modes.
cont
• - Stack pointer and base pointer are the two pointer registers whereas
the Source index and Destination index are the index group of
registers.

- They are primarily used to store relative to segment registers the

locations of offset addresses of memory locations. They serve the
purpose of being memory pointers.
• The source index and destination index are also used
as general purpose register.
• In such cases the SI and DI are implemented as
source and destination index registers.
• In stacks, data areas might exist, to be able to access
such data which contains the BP register.
Bus Operation
 Intel 8086 has a common address and data bus
which are time multiplexed.
 The two bus is commonly known as
multiplexed address and data bus.
 It provides the most efficient use of pins on the
processor.
Memory Segmentation
 Two types of memory organizations are commonly used:
 Linear addressing &
 Segmented addressing.
 Linear Addressing:
 Entire memory space is available to the processor in one linear array
 Segmented addressing:
 Available memory space is divided into segments.
 A 1Mbytes of memory in Intel 8086 is divided into 4 logical
segments with each 64 Kbytes in size.
 16-bit contents of the segment register gives the starting/base
address of a particular segment.
 To address a specific memory location within a segment we need an
offset address.
Memory Segmentation
 Note that for memory segmentation:
1. The 4 segments can overlap for small
programs and can start at the address
00000H.
2. The segment can begins at any memory
address which is divisible by 16.
 Advantages of memory segmentation:
1. Allows the memory addressing capacity to
be 1 Mbyte (though L.A is 16-bit)
2. Allows instruction code, data, and stack
portion of program to be more than 64 KB
long by using more than one code, data,
stack segment, and extra segment.
3. Facilitates use of separate memory areas
for program, data and stack.
4. Permits program relocation which is very
useful in multiprogramming.
Generation of 20-bit address
 GENERATION OF 20-BIT ADDRESS:
 The Intel 8086 generates 20-bit physical address using the
contents of segment register and the offset register associated
with it.
 Offset registers include:
 Stack pointer: Contains the 16-bit offset from the segment to
the top of stack.
• E.g. if SS =4000H and SP=9F20H, then
Physical address = SS* 10H + SP = 40000H + 9F20H = 49F20H.
 Base pointer: Can be used instead of SP in different addressing
mode.
 Source Index: Is used to hold the offset of a data word in the
data segment.
 Destination Index: String instructions always use ES and DI to
determine 20-bit physical address for the destination.
Logical address and physical address
 In Intel literature concerning the 8086, there are three types of addresses
mentioned frequently:
 The physical address,
 The offset address, and
 The logical address.
 The physical address is the 20-bit address that is actually put on the address
pins of the 8086 microprocessor and decoded by the memory interfacing
circuitry.
 This address can have a range of 00000H to FFFFFH for the 8086 CPU.
 This is an actual physical location in RAM or ROM within the 1MB memory
range.
 The offset address is a location within a 64K-byte segment range. Therefore,
an offset address can range from 0000H to FFFFH.
 The logical address consists of a segment value and an offset address.
LOGIGAL ADDRESS = SEGMENT VALUE : OFFSET VALUE
Logical
•. address and physical address
Logical address and physical address

• EXAMPLE:
Memory Segmentation
 DEFAULT AND ALTERNATE REGISTER ASSIGNMENTS
EXAMPLES
EXAMPLES
.
Segment override prefix
 SEGMENT OVERRIDE PREFIX:-
• Allows the programmer to deviate from the default
segment.
• It is an additional 8-bit code which is put in memory
before the code for the rest of the instruction and selects
the alternate segment register.
• The code byte for the segment override prefix as the
format 001XX110 where XX represents a 2 bits which is:
ES=00, CS=01, SS=10 and DS=11.
• Segment override prefix may be added to almost any
instruction in any memory addressing mode.
Quiz-1
1. Show how the flag register is affected by:
Mov BX, AAA9H
Add BX, 5557H

2. Assume that SS=4567H, DS = 1120H, SI = 2498H,

and AX = 17FEH. Show the contents of memory
locations and its contents after the execution of
MOV [SI], AX.