Microcontroller I
Introduction to Atmel AVR
MCU
Lecture II
Dr. Han-Way Huang
02/25/2025 1
Overview of the AVR Microcontroller
Introduced in 1996—Designed by two
Norwegian students: Alf-Egil and Vegard.
AVR adopts the Modified Harvard
Architecture—Data and Program are stored
in separate space but allow to also read data
from program memory.
AVR architecture defines 142 instructions.
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Overview of the AVR Microcontroller
AVR MCUs are divided into 6 categories:
Tiny AVR
MEGA AVR
Application-specific AVR.
XMEGA AVR
DA Family --- introduced in 2020
DB Family --- introduced in 2020
DD Family – introduced in 2021
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Tiny AVR
1 ~ 8 kB program memory (on-chip flash
memory)
Support between 54 to 120 instructions
Implement fewer peripheral functions
Housed in a small package (6 to 32 pins)
Highest clock rate is 20 MHz
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MEGA AVR
4 ~ 256 kB on-chip flash program
memory
Support 130 ~ 135 instructions
implement extensive peripheral
functions
Housed in a larger package (28 to 100
pins)
Highest clock rate is 20 MHz
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Application –Specific AVR
Adding special features to MEGA devices—
LCD controller, USB controller, advanced
PWM, CAN controller, and so on.
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XMEGA AVR
Program memory: 32 ~ 256 kB
Implement all 142 instructions
Implement extensive peripheral function –
use different design from the MEGA MCU
Highest clock rate is 32 MHz
Support DMA and event system
Housed in a package with 44 ~ 100 pins
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AVR DA Family
24-MHz maximum frequency
32 KB to 128 KB program memory, up to
16-KB SRAM
Programmable touch controller
12-bit ADC, 10-bit DAC
28, 32, 48, or 64-pin package
AVR DB Family
24-MHz maximum frequency
32KB to 128 KB program memory, up to 16-
KB SRAM
28, 32, 48, or 64-pin package
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AVR64DD32/28 Family
Running at up to 24 MHz
Single-cycle I/O access
Two-level interrupt controller
Two-cycle hardware multiplier
64-kB in-system programmable flash
memory
256Bytes EEPROM
One 16-bit Timer/counter type A (TCA)
One 16-bit Timer/counter type B (TCB)
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AVR XMEGA 128A1U Memory Space
Data memory and program memory are in separate
spaces.
Word address XMEGA128A1
0x00000
Application section
(bytes)
128 kB
0x0EFFF
0x0F000 Application table section
(bytes)
0x0FFFF 8 kB
0x10000 Boot section
(bytes)
0x10FFF 8 kB
Figure 1.4 XMEGA128A1Program memory
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AVR CPU Registers
AVR CPU has 32 general-purpose registers.
Six of the 32 registers form three 16-bit address pointers X,
Y, and Z.
To access program memory above 128 kB or data memory
above 64 kB, three additional registers are added: RAMPX,
Addr.
R0 0x00
R1
RAMPY, and RAMPZ. R2
0x01
0x02
···
R13 0x0D
R14 0x0E
R15 0x0F
R16 0x10
R17 0x11
···
R26 0x1A X-register low byte (XL)
R27 0x1B X-register high byte (XH)
R28 0x1C Y-register low byte (YL)
R29 0x1D Y-register high byte (YH)
R30 0x1E Z-register low byte (ZL)
R31 0x1F Z-register high byte (ZH)
Figure 2.5 AVR CPU general purpose registers
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The Status
Register SREG I: interrupt enable/disable
7 6 5 4 3 2 1 0
I T H S V N Z C T: transfer bit
Figure 2.9 The SREG register H: half carry
S: sign bit (=V N)
V: overflow
N: negative
Z: zero
C: carry
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The RAMPX, RAMPY, and RAMPZ Registers
Concatenated with X, Y, and Z, respectively, to enable
indirect addressing of the whole data memory space
above 64 kB and up to 16 MB.
To read (execute ELPM) and write (execute SPM)
program memory location above 128 kB, RAMPZ is
concatenated with Z to form a 24-bit address.
23 16 15 8 7 0
RAMPX XH XL
23 16 15 8 7 0
RAMPY YH YL
23 16 15 8 7 0
RAMPZ ZH ZL
Figure 2.6 The combined RAMPX + X, RAMPY + Y, and RAMPZ + Z registers
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Extended Indirect Register (EIND)
EIND register is added to support extended indirect
subroutine call and extended indirect jump in
devices with program memory larger than 128 kB.
The EICALL and EIJMP instructions are used to make
extended subroutine call and extended indirect jump.
EIND register is concatenated with Z.
23 16 15 8 7 0
EIND ZH ZL
Figure 2.7 The Z-pointer used by EICALL and EIJMP instructions
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RAMPD Register
The XMEGA AVR provides this register to
support direct addressing of the whole data
memory space above 64 kB (up to 16 MB).
RAMPD is concatenated with the k constant
field in the instruction.
23 16 15 0
RAMPD k
Figure 2.8 The combined RAMPD + k register
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AVR is a RISC (reduced instruction set
computer)
The AVR Addressing Modes
Used to specify operands in an instruction.
An operand in an arithmetic & logic instruction can
be a direct value, register contents.
[ ] refers to the contents of a register or a memory
location.
[r0] is the contents of register r0.
[0x1000] is the contents of data memory location
at 0x1000.
mem(addr) refers to data memory location at
addr.
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pmem(addr) refers to program memory location
Register Direct Mode
Use 5 bits (in instruction) to specify a register
operand.
add r0, r1 ; r0 [r0] + [r1]
and r16, r17 ; r16 [r16] AND [r17]
dec r1 ; r1 [r1] - 1
Immediate Mode
Use 8-bit in the instruction
ldi r16, 10 ; r16 10, destination
must be from ; r16~r31
subi r16, 5 ; r16 [r16] - 5
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I/O Direct Mode
Use 6 bits to refer to one of the first 64 I/O
registers as an operand.
User uses the register name instead of the
6-bit number to specify the I/O register.
in r0, PORTB ; r0 [PORTB] (PORTB =
0x18)
outPORTD, r1 ; PORTD [r1]
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I/O Direct Mode – (continued)
Many AVR devices have more than 64 I/O
registers.
The extended I/O memory can only be
reached by using the data memory
addressing.
I/O registers in the extended I/O memory
space must be accessed using load
(LD/LDS/LDD) and store (ST/STS/STD)
instructions.
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Use of Memory Address
AVR arithmetic and logic instructions can only operate
on registers or immediate values.
A memory location must be transferred to a register
before it can be used as an operand for arithmetic and
logic instruction.
Memory addressing modes are used to specify an
operand in data or program memory to be copied to a
register.
Memory addressing are also used to specify the
target address of a control transfer instruction
such as conditional branch, jump, or subroutine call.
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How to Specify the Address of a Memory
Location
There are two ways to specify a memory
location:
direct data mode: include the address
directly in the instruction
Indirect data mode: Place the address
in a register pointer (register pointer X,
Y, Z): there are several variations in this
mode.
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Direct Data Mode
Use a 16-bit or 7-bit value to specify the operand
address. These instructions are 16-bit or 32 bits.
lds r5, 0x2000 ; r5 [0x2000]
sts 0x2000, r2 ; mem(0x2000) [r2]
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Indirect Data Modes
Indirect data mode
Indirect data mode with postincrement
Indirect data mode with predecrement
Indirect data mode with displacement
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Indirect Data Mode
ld r2, X ; r2 [[X]]
ld r16, Y
st X, r3 ; mem([X]) [r3]
ld r8, Z ; r8 [[Z]]
Data Indirect with Post-Increment
ld r2, X+ ; r2 [[X]], X++
ld r5, Y+
st Z+, r5
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Data Indirect with Pre-Decrement
The contents of X or Y or Z is decremented
by 1 and used as an address to access data
memory.
st -X, r20; X [X] – 1 ; mem([X]) [r20]
ld r2, -X ; X [X] – 1 ; r2 [[X]]
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Data Indirect with Displacement Mode
Data memory address is formed by adding a
6-bit value from instruction to Y or Z.
ldd r8,Y+20 ; r8 [[Y] + 20] &
displacement is 6 bits
std Y+4, r2 ; mem([Y] + 4) [r2]
Data memory space
0x0000
15 0
Y or Z register
15 10 6 5 0
opcode Rr/Rd q
RAMEND
Figure 2.10 Data indirect with displacement mode
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Program memory Constant Addressing using
LPM, ELPM, and SPM
Z pointer specifies the address of the program memory to
access.
lpm r0, Z ; r0 [[Z]]
elpm r0, Z ; r0 [[RAMPZ:Z]]
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Program Memory with Post-Increment Using
LPM Z+ and ELPM Z+
Z pointer specifies the program memory address to access.
lpm r0, Z+
elpm r0,Z+
Program memory
0x0000
Opcode 6 msb
16 lsb
PC
FLASHEND
Figure 2.11 Data program addressing, JMP and CALL
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Addressing Modes for Control Flow Change
Specify the target of control flow change
Absolute target address 22-bit direct
address specified in the instruction
Indirect addressing Place the target
address in the Z pointer.
Relative address Relative to the current
PC value specifies the distance (12-bit)
from the current instruction.
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Direct Addressing, JMP and CALL
32-bit instructions
Specifies 22-bit address of the subroutine
to be called.
Indirect Program Addressing, IJMP and
ICALL
IJMP uses Z pointer to specify target
instruction to jump to.
ICALL uses Z to specify the address of the
subroutine to be called.
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Relative Program Addressing, RJMP and
RCALL
RJMP contains a 12-bit value to specify the distance of
the target to jump to.
RCALL uses a 12-bit value to specify the distance of the
subroutine to be called.
Program memory
0x0000
PC
15 12 11 0
OP k
FLASHEND
Figure 2.12 Relative program addressing, RJMP and RCALL
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Addressing Modes
1. Immediate mode
2. Register direct mode
3. Data direct mode
4. Data indirect mode
5. Data indirect with displacement
6. Data Indirect with post increment
7. Data Indirect with pre decrement
8. Program memory addressing
9. Program memory with post increment
addressing
10. Direct program memory addressing (for JMP, CALL)
11. Indirect program memory addressing (for IJMP,
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Types of Instructions
Data Transfer instructions
Arithmetic instructions—only immediate
values and registers can be the operands
Logical instructions—only immediate values
and registers can be their operands
Control flow instructions
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Data Transfer Instructions
from Register to Register
load a constant into a register
from a data memory location to a register
from a register to a data memory location
from a program memory location to a register
from a register to a program memory location
I/O operation
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Transfer from Register to Register
mov rd , r s ; rd [rs]
movw rd , r s ; rd+1:rd [rs+1]:[rs]
movw rd+1:rd, rs+1:rs ; same as the above instruction
; rd & rs must be even numbered
registers
Load a Constant into a Register
ldi Rd, k ; Rd k (d ≥ 16; 0 ≤ k ≤ 255)
ldi r16, 10 ; r16 10
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Transfer from Data Memory to a Register
Table 2.1 Instructions to transfer data from data memory to register
Instruction Description Operation
lds Rd, k Load direct from data memory Rd ¬ k
ld Rd, X Load indirect Rd ¬ [[X]]
ld Rd, X+ Load indirect and post-increment Rd ¬ [[X]]; X ¬ [X] + 1
ld Rd, -X Load indirect and pre-decrement X ¬ [X] – 1; Rd ¬ [[X]]
ld Rd, Y Load indirect Rd ¬ [[Y]]
ld Rd, Y+ Load indirect and post-increment Rd ¬ [[Y]]; Y ¬ [Y] + 1
ld Rd, -Y Load indirect and pre-decrement Y ¬ [Y] – 1; Rd ¬ [[Y]]
ldd Rd, Y+q Load indirect with displacement Rd ¬ [[Y] + q]
ld Rd, Z Load indirect Rd ¬ [[Z]]
ld Rd, Z+ Load indirect and post-increment Rd ¬ [[Z]]; Z ¬ [Z] + 1
ld Rd, -Z Load indirect and pre-decrement Z ¬ [Z] – 1; Rd ¬ [[Z]]
ldd Rd, Z+q Load indirect with displacement Rd ¬ [[Z] + q]
0 k 0xFFFF
0 q 63
0 d 31
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ldi YL, 0x00 ; Y 0x2000
ldi YH, 0x20 ; “
ld r1, Y+ ; r1 [0x2000]; Y 0x2001
ldi ZL, 0x10 ; Z 0x1010
ldi ZH, 0x10 ; “
ld r0, -Z ; Z 0x100F; r0 [0x100F]
ldi ZL, 0x00 ; Z 0x3000
ldi ZH, 0x30 ; “
ldd r0, Z+5 ; r0 [0x3005]
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Data Transfer from a Register to Data
Memory
Table 2.2 Instructions to store the contents of a register in data memory
Instruction Description Operation
sts k, Rr Store direct to data memory Mem(k) ¬ [Rr]
st X, Rr Store indirect Mem([X]) ¬ [Rr]
st X+, Rr Store indirect and post-increment Mem([X]) ¬ [Rr]; X ¬ [X] + 1
st -X, Rr Store indirect and pre-decrement X ¬ [X] – 1; mem([X]) ¬ [Rr]
st Y, Rr Store indirect Mem([Y]) ¬ [Rr]
st Y+, Rr Store indirect and post-increment Mem([Y]) ¬ [Rr]; Y ¬ [Y] + 1
st -Y, Rr Store indirect and pre-decrement Y ¬ [Y] – 1; mem([Y]) ¬ [Rr]
std Y+q, Rr Store indirect with displacement Mem([Y] + q) ¬ [Rr]
st Z, Rr Store indirect Mem([Z]) ¬ [Rr]
st Z+, Rr Store indirect and post-increment Mem([Z]) ¬ [Rr]; Z ¬ [Z] + 1
st -Z, Rr Store indirect and pre-decrement Z ¬ [Z] – 1; mem([Z]) ¬ [Rr]
std Z+q, Rr Store indirect with displacement Mem([Z] + q) ¬ [Rr]
0 k 0xFFFF
0 q 63
0 r 31
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Store Direct to Data Memory
sts 0x2000, r0 ; mem(0x2000) [r0]
Store Indirect
ldi XL, 0x00 ; X 0x1000
ldi XH, 0x10 ; “
st X, r0
Store Indirect with Post-Increment
ldi XL, 0x00 ; X 0x2000
ldi XH, 0x20 ; “
st X+, r1 ; mem (0x2000) r1; X 0x2001
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Store Indirect with Pre-Decrement
ldi YH, 0x10 ; Y 0x1000
ldi YL, 0x00 ; “
st -Y, r0 ; mem(0x0FFF) [r0]
Store Indirect with Displacement (applied
to Y or Z)
ldi ZH, 0x10 ; Z 0x1000
ldi ZL, 0x00 ; “
std Z+6, r1 ; mem (0x1006) r1
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Transfer Data between Program Memory and
a Register
Main use: define data to test your program
Table 2.3 Instructions to transfer data between a register and the program memory
Instruction Description Operation
lpm Load program memory r0 ¬ [[Z]]
lpm Rd, Z Load program memory Rd ¬ [[Z]]
lpm Rd, Z+ Load program memory and post Rd ¬ [[Z]]; Z ¬ [Z] +1
increment
elpm Extended load program memory r0 ¬ [[RAMPD:Z]]
elpm Rd, Z Extended load program memory Rd ¬ [[RAMPD:Z]]
elpm Rd,Z+ Extended load program memory and Rd ¬ [[RAMPD:Z]]; ; RAMPD:Z ¬ [[RAMPD]:[Z]] +1
post-increment
spm Store program memory pmem([RAMPD:Z]) ¬ r1:r0
spm Z+ Store program memory and post- pmem([RAMPD:Z]) ¬ R1:r0; Z¬ [Z] +2
increment by 2
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Loads the Program Memory Location pointed to by Z to r0
lpm
Loads the program memory location pointed to by Z to r10:
lpm r10, Z
Copies the contents of the program memory location
pointed to by Z to r1 and increments Z by 1:
lpm r1, Z+
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Input and Output Instructions
in r0, PORTD ; PORTD equals 0x0B (for MEGA
devices)
out PORTB, r1 ; PORTB equals to 0x05 (for MEGA
devices)
Only good for the first 64 bytes of I/O registers.
Example 2.1 Write an instruction sequence to copy the
contents of the data memory location at 0x1000 to 0x1010.
Solution:
ldi YL, 0x00 lds r0, 0x1000
ldi YH,0x10 sts 0x1010, r0
ld r0,Y
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std Y+0x10,r0
Addition Instruction
Table 2.4 AVR addition Instructions
Instruction Description Operation
add Rd, Rr Add without carry Rd ¬ [Rd] + [Rr]
adc Rd, Rr Add with carry Rd ¬ [Rd] + [Rr] + C
adiw Rd, k Add immediate to word Rd+1:Rd ¬ [Rd+1]:[Rd] + k
k = 0 ~ 63
Rd (for adiw Rd, k) can only be 24, 26, 28, 30.
How to add 10 to r1?
ldi r16, 10
add r1, r16
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Example 2.2 Write an instruction sequence to add the
contents of the data memory location at 0x1000 and
0x2000 and store the sum at 0x2010.
Solution:
lds r0, 0x1000
lds r1, 0x2000
add r0, r1
sts 0x2010, r0
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Example 2.3 Write an instruction sequence to add the
value of data memory location at 0x2000 and program
memory location at 0x1000 and leave the sum in the
register r0.
Solution:
ldi ZL, 0
ldi ZH, 0x10
lpm r1, Z
lds r0, 0x2000
add r0, r1
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Subtract Instructions
Table 2.5 AVR subtract instructions
Instruction Description Operation
sub Rd, Rs Subtract without carry rd ¬ [rd] – [rs]
subi Rd, k Subtract immediate rd ¬ [rd] - k
sbc rd, rs Subtract with carry rd ¬ [rd] – [rs] - C
sbci rd, k Subtract immediate with carry rd ¬ [rd] – k - C
sbiw rd, k Subtract immediate from word rd+1:rd ¬ [rd+1]:[rd] - k
k = 0 ~ 255 for subi rd, k and sbci rd, k
rd is r16 ~ r31 for subi rd, k & sbci rd, k
k = 0 ~ 63 for sbiw rd, k
rd can only be 24, 26, 28, 30
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Example 2.4 Write an instruction sequence to subtract 10 from the
data memory location at 0x2000.
Solution:
ldi XH, 0x20 lds r16, 0x2000
ldi XL, 0x00 subi r16, 10
ld r16, X sts 0x2000, r16
subi r16, 10
st X, r16
Example 2.5 Write a sequence of instructions to subtract 50 from the
16-bit value stored in the data memory locations 0x2000~0x2001 and
store the difference back to 0x2000~0x2001.
Solution:
ldi YH, 0x20 lds r24, 0x2000
ldi YL, 0x00 lds r25, 0x2001
ld r24, Y sbiw r24, 50
ldd r25, Y+1 sts 0x2000, r24
sbiw r24, 50 sts 0x2001, r25
st Y, r24
std Y+1, r25
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Subtract 0x2345 from r16:r17
subi r16, 0x45
sbci r17, 0x23
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