UNIT-II

SYNCHRONOUS
SEQUENTIAL LOGIC
 UNIT-III
SYNCHRONOUS SEQUENTIAL LOGIC
SYNCHRONOUS SEQUENTIAL LOGIC:
Introduction to Sequential Circuits –
Flip-Flops, operation and excitation
tables, Triggering of Flip Flop, Analysis
and design of clocked sequential circuits
– Design of Moore/Mealy models, state
minimization, state assignment, circuit
implementation- Implementation of
combinational logic/sequential logic
design using standard ICs, PROM, PLA
and PAL. 2
Sequential Logic
A Sequential circuit combinational logic circuit that consists of inputs
variable (X), logic gates (Computational circuit), and output variable (Z).
Combinational circuit produces an output based on input variable only,
but Sequential circuit produces an output based on current input and
previous input variables.
That means sequential circuits include memory elements which are
capable of storing binary information.
That binary information defines the state of the sequential circuit at that
time. A latch capable of storing one bit of information.
Types of Sequential Circuits

1. Asynchronous sequential circuit

2. synchronous sequential circuit
Asynchronous sequential circuit
 These circuit do not use a clock signal but uses the pulses of
the inputs. These circuits are faster than synchronous sequential
circuits because there is clock pulse and change their state
immediately when there is a change in the input signal.
 We use asynchronous sequential circuits when speed of operation
is important and independent of internal clock pulse.
Synchronous sequential circuit
 These circuit uses clock signal and level inputs (or
pulsed) (with restrictions on pulse width and circuit
propagation).
 The output pulse is the same duration as the clock pulse for
the clocked sequential circuits.
 Since they wait for the next clock pulse to arrive to
perform the next operation, so these circuits are
bit slower compared to asynchronous.
 Level output changes state at the start of an input pulse
and remains in that until the next input or clock pulse.
Differences between combinational circuits and
sequential circuits.
Clock Signal and Triggering
Clock signal is a periodic signal and its ON time
and OFF time need not be the same. We can
represent the clock signal as a square wave,
when both its ON time and OFF time are same.
This clock signal is shown in the following figure.
Types of Triggering
Following are the two possible types of
triggering that are used in sequential circuits.
 Leveltriggering
 Edge triggering

Level triggering
There are two levels, namely logic High and
logic Low in clock signal. Following are the
two types of level triggering.
 Positive
level triggering
 Negative level triggering
Positive level triggering
 If the sequential circuit is operated with the clock
signal when it is in Logic High, then that type of
triggering is known as Positive level triggering. It is
highlighted in below figure.

Negative level triggering

 If the sequential circuit is operated with the clock
signal when it is in Logic Low, then that type of
triggering is known as Negative level triggering. It
is highlighted in the following figure.
Edge triggering
There are two types of transitions that occur
in clock signal. That means, the clock signal
transitions either from Logic Low to Logic
High or Logic High to Logic Low.
Following are the two types of edge
triggering based on the transitions of clock
signal.
 Positive edge triggering
 Negative edge triggering
Positive edge triggering
If the sequential circuit is operated with the clock signal
that is transitioning from Logic Low to Logic High, then
that type of triggering is known as Positive edge
triggering. It is also called as rising edge triggering. It is
shown in the following figure.

Negative edge triggering

If the sequential circuit is operated with the clock signal
that is transitioning from Logic High to Logic Low, then
that type of triggering is known as Negative edge
triggering. It is also called as falling edge triggering. It is
shown in the following figure.
Flip Flop
Flip flop is a sequential circuit which
generally samples its inputs and changes its
outputs only at particular instants of time and
not continuously. Flip flop is said to be edge
sensitive or edge triggered rather than being
level triggered like latches.
Types of Flip-flop
SR Flip-Flop
D Flip-Flop
JK Flip-Flop
T Flip-Flop
SR Flip Flop
 It is basically S-R latch using NAND gates with an
additional enable input. It is also called as level triggered
SR-FF. For this, circuit in output will take place if and only
if the enable input (E) is made active. In short this circuit
will operate as an S-R latch if E = 1 but there is no change
in the output if E = 0. Circuit Diagram
Block Diagram

Truth Table
Operation
Truth Table
Present Inputs Present Next State State
State

S R Q(t) Q(t+1)
0 0 0 0 NoChange
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 x In
determine
1 1 1 x State
Characteristic Equation Excitation Table

Qn+1 = S +
State QnR’
Diagram
D-Flip FLop
D Flip Flop is the simple gated S-R latch with a NAND inverter connected
between S and R inputs. It has only one input. The input data is appearing
at the output after some time. Due to this data delay between i/p and o/p, it
is called delay flip flop. S and R will be the complements of each other due
to NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will
never appear. This problem is avoid by SR = 00 and SR = 1 conditions.
Block Diagram Circuit Diagram

Truth Table
Excitation table for T Flipflop
JK Flip FLop
 JK flip-flop is the modified version of SR flip-flop. It
operates with only positive clock transitions or negative
clock transitions. The circuit diagram of JK flip-flop is
shown in the following figure.
Circuit Diagram

Truth Table
Present Inputs Present Next State State
State

S R Q(t) Q(t+1)
0 0 0 0 NoChange
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0
Characteristic Equation Excitation Table

Qn Qn+1 J K

0 0 0 X
Qn+1 = Q’nJ + QnK’
State Diagram 0 1 1 X

1 0 X 1

1 1 X 0
T-FlipFLop
Toggle flip flop is basically a JK flip flop with J and K
terminals permanently connected together. It has only
input denoted by T as shown in the Symbol Diagram. The
symbol for positive edge triggered T flip flop is shown in
the Block Diagram. Circuit Diagram
Block Diagram

Operation
Truth Table
Excitation table for T Flipflop
Conversion of Flip flop
SR Flip-Flop to other Flip-Flop Conversions
Following are the three possible conversions of
SR flip-flop to other flip-flops.
 SR flip-flop to D flip-flop
 SR flip-flop to JK flip-flop

 SR flip-flop to T flip-flop
SR flip-flop to D flip-flop
SR flip-flop to JK flip-flop
D Flip-Flop to other Flip-Flop Conversions

Following are the three possible conversions

of D flip-flop to other flip-flops.
 D flip-flop to T flip-flop
 D flip-flop to SR flip-flop
 D flip-flop to JK flip-flop
D flip-flop to T flip-flop conversion
D-FF to SR-FF Conversion
In this type of conversion, D is the actual i/p of the flip flop where
S & R are the external i/ps.There are Eight possible combinations
are obtained from the external i/ps S, R & Qp. Nevertheless, since
the combination of S=R=1 is unacceptable, the values of D and
Qp+1 are taken as “don’t care”.
D-Flip Flop to JK-Flip Flop Conversion
In this type of flip flop conversion, J & K are the external
i/ps of the flip flop where D is the actual input. The eight
combinations can make by using J, K and Qp that is shown
in the conversion table below. D is stated in terms of J, K &
Qp. The Karnaugh map D in terms of J, K & Qp, conversion
table and the logic diagram of the D-FF to JK-FF is shown
below.
JK Flip-Flop to other Flip-Flop Conversions

 JK flip-flop to T flip-flop
 JK flip-flop to D flip-flop
 JK flip-flop to SR flip-flop
JK to SR flipflop conversion
The conversion of the JK-FF to SR-FF is opposite to the SR-FF to
JK-FF. Here S & R will be the external i/ps to J & K, that is shown
in the below logic diagram, J & K will be the o/ps of the
combinational circuit. So, the J and K values have to be acquired
in terms of S, R & Qp. The logic diagram is shown below. The
conversion table for flip flop to be written in terms of S, R, Qp,
Qp+1, J & K. There are eight possible combinations for two i/ps S
and R.
JK-Flip Flop to T-Flip Flop Conversion

In this type of conversion, J & k are the actual i/ps of the

flip flop where K is considered as the external i/p. Four
combinations are created by T, Qp, J & K that are expressed
in terms of T & Qp. The Karnaugh map, the logic diagram
and conversion table, are given below.
JK flip-flop to D flip-flop
In this type of flip flop conversion, J&K are the actual
inputs where D is the external input of the flip flop. The
four combinations of the flip flop will be done by using D &
Qp, and in terms of these two J&K are expressed. The
conversion table with four combinations, JK-FF to D-FF
conversion logic diagram and Karnaugh map for J & K in
terms of D & are shown below.
T Flip-Flop to other Flip-Flop Conversions

Following are the three possible conversions

of T flip-flop to other flip-flops.
 T flip-flop to D flip-flop
 T flip-flop to SR flip-flop
 T flip-flop to JK flip-flop
T flip-flop to D flip-flop conversion
State Reduction Techniques
 The reduction of the number of flip-flops in a sequential
circuit is referred to as the state reduction problem. State-
reduction algorithms are concerned with procedures for
reducing the number of states in a state table, while
keeping the external input-output requirements
unchanged. A synchronous sequential circuit is also called
as Finite State Machine (FSM), if it has finite number of
states. There are two types of FSMs.
 Mealy State Machine

 Moore State Machine

Mealy State Machine
A Finite State Machine is said to be Mealy
state machine, if outputs depend on both
present inputs & present states. The block
diagram of Mealy state machine is shown in
the following figure.
Block Diagram State
Diagram
Moore State Machine
A Finite State Machine is said to be Moore
state machine, if outputs depend only on
present states. The block diagram of Moore
state machine is shown in the following
figure.
Block Diagram State
Diagram
Example problems
Two states are said to be
equivalent if, for each
member of the set of
inputs, they give exactly the
same output and send the
circuit either to the same
state or to an equivalent
state
Design Procedure
Step 1: Determine the number of Flipflop
needed. if n represents number of flip flop 2n
≥ N(No of States in counter).
Step 2: Choose the type of flip flop to be used.
Step 3: Use Excitation table for selected flip flop
determine the excitation table for the counter.
Step 4: use K-map to derive the flip flop input
functions
Step 5: Draw the logic diagram
Synchronous problems
Design a synchronous counter with states 0, 1, 2, 3, 0, 1, ………using
JK Flip-Flops.

Step 1: 2n ≥ N= 3 , 22 ≥ 2
Step 2: JK Flip flop
Step 3: Excitation Table for Counter:

Step 4:
Step 5: Logic Diagram
Design a MOD-7 synchronous counter using JK Flip-
Flops. Write excitation table and state table.
Soln:
2n ≥ N= 7 Therefore, 3 Flip-Flops
are required.
23> 8.
State Diagram: State Table:
Excitation Table:Present State Next State
000 001
Present State Next State Inputs
001 010

010 011 Qn Qn+1 J K

011 100

100 101 0 0 0 x

101 110 0 1 1 x

110 000 1 0 x 1

1 1 x 0
Excitation Table for Counter:
Present State Next State Flip-Flop Inputs

QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA

0 0 0 0 0 1 0 x 0 x 1 x

0 0 1 0 1 0 0 x 1 x x 1

0 1 0 0 1 1 0 x x 0 1 x

0 1 1 1 0 0 1 x x 1 x 1

1 0 0 1 0 1 x 0 0 x 1 x

1 0 1 1 1 0 x 0 1 x x 1

1 1 0 0 0 0 x 1 x 1 0 x
K-Map Specification
Logic Diagram
Assignment Problems
1.Design a MOD-10 synchronous counter using JK Flip-Flops.
Write excitation table and state table.
2. Design a 3 bit (MOD 8) Synchronous UP/DOWN counter.
3. Design a synchronous counter for
Avoid lockout condition. Use JK type design.
4. Using JK Flip-Flops, design a synchronous counter counts in
the sequence, 000, 001, 010, 011, 100, 101, 110, 111, 000.
5. Solve state reduction techniques:
 Combinational PLDs
 A combinational PLD is an integrated circuit with
programmable gates divided into an AND array and
an OR array to provide an AND-OR sum of product
implementation.
 PROM: fixed AND array constructed as a
decoder and programmable OR array.
 PAL: programmable AND array and fixed OR
array.
 PLA: both the AND and OR arrays can be
programmed.

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Combinational PLDs

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 7-6. Programmable Logic Array
 PLA is a programmable logic device that has both Programmable
AND array & Programmable OR array. Hence, it is the most
flexible PLD. The block diagram of PLA is shown in the
following figure.

 The decoder in PROM is replaced by an array of AND gates that can be

programmed to generate any product term of the input variables.
 The product terms are then connected to OR gates to provide the sum of
products for the required Boolean functions.

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PLA
F1 = AB’+AC+A’BC’
F2 = (AC+BC)’

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 Example 7-2
Implement the following two Boolean functions with
a PLA: F1(A, B, C) = ? (0, 1, 2, 4)
F2(A, B, C) = ? (0, 5, 6, 7)

The two functions are simplified in the maps of Fig.7-15

1
elements
 Both the true and
complement of the
functions are simplified in
sum of products.
 We can find the same
terms from the group
terms of the functions of
F1, F1’,F2 and F2’ which will
make the minimum
terms.

F1 = (AB + AC +
BC)’ F2 = AB + AC
+ A’B’C’
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PLA implementation

AB

AC

BC

A’B’

C’

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Programmable Array Logic (PAL)
PAL is a programmable logic device that has
Programmable AND array & fixed OR array. The
advantage of PAL is that we can generate only the
required product terms of Boolean function
instead of generating all the min terms by using
programmable AND gates. The block diagram of
PAL is shown in the following figure.
 Example
w(A, B, C, D) = ? (2, 12, 13)
x(A, B, C, D) = ? (7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ? (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = ? (1, 2, 8, 12, 13)

Simplifying the four functions as following Boolean

functions: w = ABC’ + A’B’CD’

x = A + BCD
w = A’B + CD + B’D’
w = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ +
A’B’C’D
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 PAL Table
 z has four product terms, and we can replace by w
with two product terms, this will reduce the number
of terms for z from four to three.

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PAL implementation

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Fuse map for example

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