Shift Registers and Shift Counters

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 Registers
• A collection of flip-flops taken as an entity.
• Function: Hold information within a digital system
so that it is available to the logic elements during
the computing process.
• Each combination of stored information is known
as the state or content of the register.
• Shift register: Registers that are capable of
moving information upon the occurrence of a
clock-signal.
 Unidirectional
 bidirectional

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 Registers
• Two basic ways in which information can be
entered/outputted
 Parallel: All 0/1 symbols handled simultaneously.
Require as many lines as symbols being transferred.
 Serial: Involves the symbol-by-symbol availability of
information in a time sequence.
• Four possible ways registers can transfer
information:
 Serial-in/serial-out
 Serial-in/parallel-out
 Parallel-in/parallel-out
 Parallel-in/serial-out

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Serial-in, Serial-out, Unidirectional
Shift Register

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4- bit (1010) being entered serially into Serial In, Serial Out Shift Register
(SISO)
Serial In, Serial Out Shift Register
(SISO)

FF0 FF1 FF2 FF3

Clear 0 0 0 0
1010 0 0 0 0
101 0 0 0 0 0
10 1 0 0 0 00
1 0 1 0 0 000
Clear 1 0 1 0 0000
 Serial-in, Parallel-out
Unidirectional Shift Register

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 Parallel-in, Parallel-out
Unidirectional Shift Register
A four-bit parallel in - serial out shift register is shown below.
The circuit uses D flip-flops and NAND gates for entering data
(ie writing) to the register.

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 Parallel-in, Parallel-out
Unidirectional Shift Register

• D0, D1, D2 and D3 are the

parallel inputs, where D0 is the
most significant bit and D3 is
the least significant bit. To
write data in, the mode control
line is taken to LOW and the
data is clocked in. The data
can be shifted when the mode
control line is HIGH as SHIFT
is active high.

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 4-bit parallel in/serial out shift register
(PISO)

When signal = 1,
SHIFT

When signal = 0,
 LOAD
 4-bit parallel in/serial out shift register
(PISO)

When signal
= 0,
LOAD

G1 – G3
enabled
 4-bit parallel in/serial out shift register
(PISO)

When signal
= 1,
SHIFT

G4 – G6
enabled
 Let’s try to trace this one first…
1 0 1 0
Assume
that the
signal has
values
011011 for
6 respective
clock cycle

For the parallel data input

Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0
 Let’s try to trace this one first…
0 1 1 1
0 0 0
CLK 1,
Signal = 0
G1 – G3
Will get
value = 1
G4 – G6
Will get
value = 0

Referring to the AND gate theory,

All gates that receives “0” values at shift/load can be
ignored.
 Let’s try to trace this one first…

1 1 1

1 0 1 0

Now, AND the shift/load value with

Respective data that goes into G4, G5, G6
 How do you put it in table?
For the parallel data input
Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0
Active
Clk Shift/Load signal Q0 Q1 Q2 Q3
0 Clear Clear 0 0 0 0
1 0 LOAD 1 0 1 0
2 1 SHIFT 1 1 0 1
3 1 SHIFT 1 1 1 0
4 0 LOAD 1 0 1 0
5 1 SHIFT 1 1 0 1
6 1 SHIFT 1 1 1 0
 Parallel In - Parallel Out
Unidirectional Shift Registers
• For parallel in - parallel out shift registers, all data
bits appear on the parallel outputs immediately
following the simultaneous entry of the data bits.
The following circuit is a four-bit parallel in -
parallel out shift register constructed by D flip-
flops.

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Bidirectional Shift Registers

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 Bidirectional Shift Register
• Here a set of NAND gates are
configured as OR gates to
select data inputs from the
right or left adjacent
bistables, as selected by the
LEFT/RIGHT control line.
• The animation shown
performs right shift four
times, then left shift four
times. Notice the order of
the four output bits are not
the same as the order of the
original four input bits. They
are actually reversed!

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 Universal Shift Register

A bidirectional shift register. Capable of shifting contents either left or right

depending upon the signals present on appropriate control input lines.
Universal shift register: Depending on the signal values on the select lines of the
multiplexers, the register can retain its current state, shift right, shift left or be loaded
in parallel. Each operation is the result of a positive edge on the clock line. 20
 Shift Register Counters
• Two of the most common types of shift
register counters are introduced here:
the Ring counter and the Johnson
counter.
• They are basically shift registers with
the serial outputs connected back to
the serial inputs in order to produce
particular sequences. These registers
are classified as counters because they
exhibit a specified sequence of states.

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 Ring Counter
• A ring counter is basically a circulating shift register in
which the output of the most significant stage is fed back to
the input of the least significant stage. The following is a 4-
bit ring counter constructed from D flip-flops. The output
of each stage is shifted into the next stage on the positive
edge of a clock pulse. If the CLEAR signal is high, all the
flip-flops except the first one FF0 are reset to 0. FF0 is
preset to 1 instead.

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 Ring Counter
• Ring counters are implemented using
shift registers. It is essentially a
circulating shift register connected so
that the last flip-flop shifts its value
into the first flip-flop. There is usually
only a single 1 circulating in the
register, as long as clock pulses are
applied. (Starts 1000->0100->0010-
>0001 repeat)
• Since the count sequence has 4
distinct states, the counter can be
considered as a mod-4 counter. Only
4 of the maximum 16 states are used,
making ring counters very inefficient
in terms of state usage. But the major
advantage of a ring counter over a
binary counter is that it is self-
decoding. No extra decoding circuit
is needed to determine what state the
counter is in.

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Example : A 10-bit Ring Counter
 Assume initial state : 0000000101
 n-bit Ring Counter

Start control signal, which presets the left-most flip-flop

to 1 and clears the others to 0.

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 Counters Based on Shift
Registers

Ring counter. Not efficient in the number of

flip-flops used, but provides a decoded
output. To detect any particular state in the
counting sequence it is only necessary to
interrogate the output of a single flip-flop.
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Johnson Counter

Johnson counters are a variation of standard

ring counters, with the inverted output of the
last stage fed back to the input of the first stage.
They are also known as twisted ring counters.
An n-stage Johnson counter yields a count
sequence of length 2n, so it may be considered
to be a mod-2n counter. The circuit above
shows a 4-bit Johnson counter. The state
sequence for the counter is given in the table as
well as the animation on the left.

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 Clock Pulse
FFA FFB FFC FFD
No
0 0 0 0 0
Truth Table for a 4-bit Johnson 1 1 0 0 0
Ring Counter 2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

As well as counting or rotating data around a continuous loop, ring

counters can also be used to detect or recognize various patterns or
number values within a set of data. By connecting simple logic gates such
as the AND or the OR gates to the outputs of the flip-flops the circuit can
be made to detect a set number or value. Standard 2, 3 or 4-stage
Johnson ring counters can also be used to divide the frequency of the
clock signal by varying their feedback connections and divide-by-3 or
divide-by-5 outputs are also available.
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Example : Five-bit Johnson
counters
 Johnson Counter
• Again, the apparent disadvantage of this counter is that the maximum
available states are not fully utilized. Only eight of the sixteen states are
being used.
• Beware that for both the Ring and the Johnson counter must initially be
forced into a valid state in the count sequence because they operate on a
subset of the available number of states. Otherwise, the ideal sequence
will not be followed.
• To initialize the operation of the Johnson counter, it is necessary to reset
all flip-flops, as shown in the figure. Observe that neither the Johnson nor
the ring counter will generate the desired counting sequence if not
initialized properly.

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Counters Based on Shift
Registers

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Counters Based on Shift
Registers

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 Applications of Shift Registers
Shift registers can be found in many applications. Here
is a list of a few
• To produce time delay
The serial in -serial out shift register can be used as a
time delay device. The amount of delay can be controlled
by:
> the number of stages in the register
> the clock frequency
• To convert serial data to parallel data
A computer or microprocessor-based system commonly
requires incoming data to be in parallel format. But
frequently, these systems must communicate with
external devices that send or receive serial data. So,
serial-to-parallel conversion is required. As shown in the
previous sections, a serial in - parallel out register can
achieve this.

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 Applications of Shift Registers
• To simplify combinational logic
The ring counter technique can be effectively utilized to
implement synchronous sequential circuits. A major
problem in the realization of sequential circuits is the
assignment of binary codes to the internal states of the
circuit in order to reduce the complexity of circuits
required. By assigning one flip-flop to one internal
state, it is possible to simplify the combinational logic
required to realize the complete sequential circuit.
When the circuit is in a particular state, the flip-flop
corresponding to that state is set to HIGH and all other
flip-flops remain LOW.

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