ARM (Advanced/ACRON

RISC Machines)
Processors

By: Dr. Dharmendra Kumar

Assistant Professor
EIED, TIET Patiala, Punjab, India
ARM (Advanced/ACRON RISC Machines) Processors
• The ARM architecture incorporated a number of features from the Berkeley RISC design, but a number
of other features were rejected. Those that were used were:
• a load-store architecture;
• fixed-length 32-bit instructions;
• 3-address instruction formats.

• The features that were employed on the Berkeley RISC designs which were rejected by the ARM
designers were:

• Register windows:The principal problem with register windows is the large chip area occupied by the large number of registers.
This feature was therefore rejected on cost grounds, although the shadow registers used to handle exceptions on the ARM are not
too different in concept.
• Delayed branches: Branches cause pipelines problems since they interrupt the smooth flow of instructions. Most RISC
processors ameliorate the problem by using delayed branches where the branch takes effect after the following instruction has
executed.
• Single-cycle execution of all instructions: Although the ARM executes most data processing instructions in a single clock
cycle, many other instructions take multiple clock cycles.
ARM core dataflow model.
ARM core dataflow model.
ARM core dataflow model.
Current Program Status Register (CPSR)
ARM instruction set
Arithmetic Instructions
Comparison Instructions
Load-Store Instructions
ARM Exception Model Overview

• An exception is defined in the ARM specification as “a condition that changes the normal flow of control in a program”.

• You will often see the terms “interrupt” and “exception” used interchangeably. However, in the ARM documentation,
“interrupt” is used to describe a type of “exception”.
• Exceptions are identified by the following pieces of information:

• Exception Number - A unique number used to reference a particular exception (starting at 1). This number is also
used as the offset within the Vector Table where the address of the routine for the exception can be found. The routine
is usually referred to as the Exception Handler or Interrupt Service Routine (ISR) and is the function which runs when
the exception is triggered. The ARM hardware will automatically look up this function pointer in the Vector Table
when an exception is triggered and start executing the code.

• Priority Level / Priority Number - Each exception has a priority associated with it. For most exceptions this number
is configurable. Counter-intuitively, the lower the priority number, the higher the precedence the exception has. So for
example if an exception of priority level 2 and level 1 occur at the same time, the level 1 exception will be run first.
When we say an exception has the “highest priority”, it will have the lowest Priority Number. If two exceptions have
the same Priority Number, the exception with the lowest Exception Number will run first.

• Synchronous or Asynchronous - As the name implies, some exceptions will fire immediately after an instruction is
executed (i.e SVCall). These exceptions are referred to as synchronous. Exceptions that do not fire immediately after a
particular code path is executed are referred to as asynchronous.
States of exception
• Pending - The MCU has detected the exception and scheduled it but
has not yet invoked the handler for it.
• Active - The MCU has started to run the exception handler but not
yet finished executing it. It’s possible for the exception to have been
“pre-empted” by a higher priority handler and be in this state.
• Pending & Active - Only possible for asynchronous exceptions, this
basically means the exception was detected by the MCU again while
processing an earlier detected version of the same exception.
• Inactive - The exception is neither pending nor active.
Entering and exiting an exception handler
Here are the steps that the ARM processor does to handle an exception:
• Preserve the address of the next instruction.
• Copy CPSR to the appropriate SPSR, which is one of the banked registers for each mode of
operation.
• Force the CPSR mode bits to a value depending on the raised exception.
• Force the PC to fetch the next instruction from the exception vector table.
• Now the handler is running in the mode associated with the raised exception.
• When handler is done, the CPSR is restored from the saved SPSR.
• PC is updated with the value of (LR – offset) and the offset value depends on the type of the
exception.

And when deciding to leave the exception handler, the following steps occurs:
• Move the Link Register LR (minus an offset) to the PC.
• Copy SPSR back to CPSR, this will automatically changes the mode back to the previous one.
• Clear the interrupt disable flags (if they were set).
 Interrupt handling schemes
• Non-nested interrupt handling
Interrupts are disabled until control is returned back to the interrupted
task. So only one interrupt can be served at a time and that is why this
scheme is not suitable for complex embedded systems which most
probably have more than one interrupt source and require concurrent
handling.
• Initially interrupts are disabled, When IRQ exception is raised and the
ARM processor disables further IRQ exceptions from occurring.
• The mode is changed to the new mode depending on the raised
exception.
• The register CPSR is copied to the SPSR of the new mode. Then the PC
is set to the correct entry in the vector table and the instruction there
will direct the PC to the appropriate handler. Then the context of the
current task is saved a subset of the current mode non banked
register.
• Then the interrupt handler executes some code to identify the
interrupt source and decide which ISR will be called. Then the
appropriate ISR is called.
• And finally the context of the interrupted task is restored, interrupts
are enabled again and the control is returned to the interrupted task.
Nested interrupt handling Prioritized simple interrupt handling
• Built in Exceptions
• Reset - This is the routine executed when a chip comes out of reset. More details can
be found within the Zero to main() series of posts.
• Non Maskable Interrupt (NMI) - As the name implies, this interrupt cannot be
disabled. If errors happen in other exception handlers, a NMI will be triggered. Aside
from the Reset exception, it has the highest priority of all exceptions.
• HardFault - The catchall for assorted system failures that can take place such as
accesses to bad memory, divide-by-zero errors and illegal unaligned accesses. It’s the
only handler for faults on the ARMv6-M architecture but for ARMv7-M & ARMv8-
M, finer granularity fault handlers can be enabled for specific error classes (i.e
MemManage, BusFault, UsageFault). 2
• SVCall - Exception handler invoked when an Supervisor Call (svc) instruction is
executed.
• PendSV & SysTick - System level interrupts triggered by software. They are typically
used when running a RTOS to manage when the scheduler runs and when context
switches take place
External Interrupts
• ARM cores also support interrupt lines which are “external” to the core itself. These
interrupt lines are usually routed to vendor-specific peripherals on the MCU such as
Direct Memory Access (DMA) engines or General Purpose Input/Output Pins
(GPIOs). All of these interrupts are configured via a peripheral known as the Nested
Vectored Interrupt Controller (NVIC).
• The Exception Number for external interrupts starts at 16. The ARMv7-M reference
manual has a good graphic which displays the Exception number mappings: