Digital Logic Design

ELCT201
Spring 2024

Tutorial 7
Sequential circuits: Latches and Flip Flops

1
 Combinational vs. Sequential

i/p
Combinational Circuit
o/p

Memory
Elements

Any Memory element can be identified by characteristic

table, characteristic equation, and/or excitation table

2
 Latches

• SR Latch
– S’R’ Latch
– SR Latch with Control
• D Latch (Transparent Latch)
• Other Latches
– JK
– T

3
 SR Latch:
for RESET • It consists of two cross coupled NOR gates
for SET
SR Ch./c table:
SS R RQ(t+1)
Q(t+1)
Q’(t+1)
Operation
Operation

00 0 0 Q(t) Q(t) Q’(t)No change

No change

00
0 1 1
1 0 0 1 Reset Reset
Reset Q
11
1 0 0
0 1 1 0 Set
SetSet
1 1 Undefined
11 1 1 - - - Undefined
Undefined

Q’

R Q

S Q’
 SR Latch

Q
0 010 11 00

Q’

1 0 00 00 11

5
 S’R’ Latch
• It consists of two cross coupled NAND gates
S’R’ Ch./c table:
S’ R’ Q(t+1)
0 0 - undefined
0 1 1 Set
1 0 0 Rest
1 1 Q(t) No change

S’ Q

R’ Q’

6
 SR Latch with a control

SR with control Ch./c table:

C S R Q(t+1)
0 X X Q(t) No change S’R’ latch

1 0 0 Q(t) No change 1
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 - Undefined
0
1

S Q S’R’ Ch./c table:

C S’ R’ Q(t+1)
R Q’ 0 0 - undefined
0 1 1 Set
1 0 0 Rest
1 1 Q(t) No change

7
 D Latch (The transparent Latch)

D - Ch./c table: SR latch with control

C D Q(t+1)
S’R’ latch
0 x Q(t) No change
0 0
1 0 0 Reset
1 1 1 set
1

D - Ch./c eq.:
Q(t+1) = D 1

D Q SR with control Ch./c table:

C S R Q(t+1)
0 X X Q(t) No change
C Q’
1 0 0 Q(t) No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 - Undefined

8
 JK Latch

JK Ch./c table: JK truth table: K-map:

J K Q(t+1) J K Q Q(t+1) KQ
K
J
0 0 Q(t) No change 0 0 0 0 1
0 1 0 Reset 0 0 1 1
J 1 1 1
1 0 1 Set
0 1 0 0
1 1 Q’(t) Complement Q
0 1 1 0
1 0 0 1 JK Ch./c equation:
1 0 1 1 Q(t+1) = JQ’ + K’Q
1 1 0 1
1 1 1 0
J Q

K Q’

9
 T Latch

T - Ch./c table: T truth table: T - Ch./c equation:

T Q(t+1) T Q Q(t+1) Q(t+1) = TQ’ + T’Q
0 Q(t) No change 0 0 0 =T Q
1 Q’(t) complement 0 1 1
1 0 1
1 1 0

T Q
Q
T D Q
Q’

C Q’
 Latch Timing Problem

• Latch state keep changing as Ch./c table:

Latch-Q
D C D Q(t+1)
long as the clock remains D-Latch
0 x Q(t)
active and thus due to
1 0 0
uncertainty latches can not be
1 1 1
used as storage elements! CLK

Example:
0 1 2 3 4 5
CLK
D

N.B.:
• The Clock Pulses
problem with latches is that it responds to a change in the
level of a clock pulse+ve
 LATCH
pulse TIMING PROBLEM

-ve pulse
 Flip Flops

• FF are constructed in such a way to make them operate

properly when they are part of a sequential circuit by
triggering the change only at signal transition.
Master Slave FF: Employ 2 latches in a special configuration that
N.B: Signal Transition
isolates the o/p of FF from being affected while i/p is changing
+ve edge

-ve edge

D Latch-Q FF-Q
D-Latch D-Latch
(Master) (Slave)

CLK
 Flip Flops Solving The Latch Timing Problem
D Ch./c table:
D Latch-Q FF-Q
C D Q(t+1)
D-Latch D-Latch
(Master) (Slave)
0 x Q(t)
1 0 0

CLK 1 1 1

Example Cont’d:
0 1 2 3 4 5
CLK

Latch-Q
D(slave latch)

CLK’
CLK(slave latch)
FF-Q

N.B.: Ch./c table and equation doesn’t change for latch

and FF: only their timing diagram does!
 Latch Timing Solution using Flip Flops

D Latch-Q FF-Q
D-Latch D-Latch
D (Master) (Slave)

CLK

CLK

0 1 2 3 4 5
CLK
D

Latch-Q

CLK’

FF-Q
 Flip Flops
– FF that triggers only during a signal transition and is disabled
during the rest of the clock pulse duration
• (-ve) edge triggered FF
• (+ve) edge triggered FF

D
D

CLK
CLK

D D
D-Latch D-Latch D-Latch D-Latch
(Master) (Slave) (Master) (Slave)

CLK CLK
 Sheet 7
• Problem 2:
• Show how a JK-FF is constructed from 2 JK-Latches in such a
way to make them operate properly when they are part of a
sequential circuit equivalent to triggering the change at signal
positive transition

J JK-Latch JK-Latch
(Master) (Slave)
K

CLK
 Sheet 7
• Problem 3:
• A PN Flip flop has four operations: clear to 0, no change, complement, and set to 1,
when inputs P and N are 00, 01, 10 and 11, respectively:
a) Tabulate the characteristic table
NQ N
b) Derive the characteristic equation P
m m m m
c) Tabulate the excitation table o 1
13 2

d) Show how the PN can be constructed from a D-FF P

m4
1 m 5 m
17 m 6
1
Q
(a) PN Ch./c table: PN truth table: (b) PN Ch./c eq.:
P N Q(t+1) P N Q Q(t+1) Q(t+1)= PQ’ + NQ
0 0 0 Clear to 0 0 0 0 0
0 1 Q(t) No change 0 0 1 0
1 0 Q’(t) Complement 0 1 0 0
1 1 1 Set to 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
 Sheet 7
• Problem 3:
• A PN Flip flop:
c) Tabulate the excitation table
d) Show how the PN can be constructed from a D-FF
(a) PN Ch./c table: PN truth table: (b) PN Ch./c eq.:
P N Q(t+1) P N Q Q(t+1) Q(t+1)= PQ’ + NQ
0 0 0 0 0 0 0
0 1 Q(t) 0 0 1 0
1 0 Q’(t)
0 1 0 0
1 1 1 (c) PN Excitation Table
0 1 1 1 Q Q(t+1) P N
1 0 0 1
0 0 0 X
1 0 1 0
0 1 1 X
1 1 0 1
1 0
1 1 1 1
1 1
 Sheet 7
• Problem 3:
• A PN Flip flop:
c) Tabulate the excitation table
d) Show how the PN can be constructed from a D-FF
(a) PN Ch./c table: PN truth table: (b) PN Ch./c eq.:
P N Q(t+1) P N Q Q(t+1) Q(t+1)= PQ’ + NQ
0 0 0 0 0 0 0
0 1 Q(t) 0 0 1 0
1 0 Q’(t)
0 1 0 0
1 1 1 (c) PN Excitation Table
0 1 1 1 Q Q(t+1) P N
1 0 0 1
0 0 0 X
1 0 1 0
0 1 1 X
1 1 0 1
1 0 X 0
1 1 1 1
1 1 X 1
 Sheet 7
• Problem 3:
• A PN Flip flop:
c) Tabulate the excitation table
d) Show how the PN can be constructed from a D-FF
(a) PN Ch./c table: PN truth table: (b) PN Ch./c eq.:
P N Q(t+1) P N Q Q(t+1) Q(t+1)= PQ’ + NQ
0 0 0 0 0 0 0
0 1 Q(t) 0 0 1 0
1 0 Q’(t)
0 1 0 0
1 1 1 (c) PN Excitation Table
0 1 1 1 Q Q(t+1) P N
1 0 0 1
0 0 0 X
1 0 1 0
0 1 1 X
1 1 0 1
1 0 X 0
1 1 1 1
1 1 X 1
 Sheet 7
• Problem 3:
• A PN Flip flop:
c) Tabulate the excitation table
d) Show how the PN can be constructed from a D-FF
(a) PN Ch./c table:eq.:
D Ch./c PN truth table: PN Ch./c
(b) PN
eq.:Ch./c eq.:
P N Q(t+1) D
Q(t+1)=  (1) P N Q Q(t+1) Q(t+1)=
Q(t+1)=
PQ’ + PQ’
NQ + NQ
0 0 0 0 0 0 0
0 1 Q(t) From Eq,(1)
0 and
0 (2):
1 0
1 0 Q’(t) D = PQ’ +0 NQ1 0 0
1 1 1 (c) PN Excitation Table
0 1 1 1 Q Q(t+1) P N
1 0 0 1
0 0 0 X
P 1 0 1 0
0 1 1 X
1 1 0 1D Q
N 1 0 X 0
1 1 1 1
1 1 X 1
Q’

CLK
 How to implement any flip flop using another

• Equate the 2 characteristics equations together, trying to map

the inputs of 1 flip flops to the other.
• Example: Implement T Flip –Flop using JK Flip-Flop
T Ch./c eq.: JK Ch./c eq.:
Q(t+1)= TQ’ + T’Q  (1) Q(t+1)= JQ’ + K’Q

From Eq.(1) and Eq.(2):

TQ’ + T’Q = JQ’ + K’Q
T=J T=K

T J Q

K Q’

Clk