Fabrication and

Manufacturing (Basics)
• Batch processes • Silicon is neat stuff
– Fabrication time independent – Oxide protects things from
of design complexity impurities
• Standard process – Can be etched selectively on
– Customization by masks silicon or metal
– Each mask defines geometry • Can be doped
on one layer – Add P or As impurities
– Lower-level masks define
transistors
– Higher-level masks define
wiring

Mrs . Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 1

 CMOS Fabrication
• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited or
etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 2

 Making Chips
Masks

Processed
Chemicals Processing wafer Chips

Wafers

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 3

 Inverter Cross-section
• Typically use p-type substrate for nMOS
transistors
• Requires n-well for body of pMOS
transistors
GND
A Y VDD SiO2

n+ diffusion

p+
n+ n+ p+ p+

n well diffusion
p substrate
polysilicon

nMOS transistor pMOS transistor metal1

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 4

 Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
• Use heavily doped well and substrate contacts /
taps A
GND
Y VDD

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 5

 Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line

GND
VDD
nMOS transistor pMOS transistor
substrate tap well tap

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 6

 Detailed Mask Views
n well

• Six masks
– n-well Polysilicon

– Polysilicon
– n+ diffusion n+ Diffusion

– p+ diffusion p+ Diffusion

– Contact Contact

– Metal

Metal

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 7

 Basic Processing Steps
• N-diffusion created by doping regions of the
substrate
• Poly and metal are laid over the substrate, with
oxide to insulate them from substrate and each
other
• Wires are added in layers, alternating with
oxide
• Vias are cut in the oxide

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 8

 Fabrication Steps
• Features are patterned on a wafer by a
photolithographic process
– Photo-light lithography, n. process of printing from a plane surface
on which image to be printed is ink-receptive and the blank area is
ink-repellant
• Cover the wafer with a light-sensitive, organic material
called photoresist
• Expose to light with the proper pattern (mask)
• Patterns left by photoresist can be used to control where
oxide is grown or materials are placed on surface of wafer

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 9

 Fabrication Steps
• Layout contains information on what patterns have
to made on the wafer
• Masks are created using the layout information
provided by the designer
• Procedure involves selective removal of the
oxide
– Coat the oxide with photoresist, polymerized by UV
light (applied through mask)
– Polymerized photoresist dissolves in acid
– Photoresist itself is acid-resistant

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 10

 Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 11

 Oxidation
• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation
furnace

SiO2

p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 12

 Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 13

 Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist
SiO2

P-substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 14

 Etch
• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

Photoresist
SiO2

P-substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 15

 Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

P-substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 16

 n-well
• n-well is formed with diffusion or ion
implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed
Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter SiO2

exposed Si
P-substrate n well

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 17

 Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

N-well
p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 18

 Polysilicon
• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon
layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide

n well
p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 19

 Polysilicon Patterning
• Use same lithography process to pattern
polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 20

 Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 21

 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 22

 N-diffusion cont.
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+
n well
p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 23

 N-diffusion cont.
• Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 24

 P-Diffusion
• Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

P-Substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 25

 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 26

 Metalization
• Sputter on aluminum (copper) over whole wafer
• Pattern to remove excess metal, leaving wires

M etal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

N-well
P-substrate

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 27

Basic Processing Steps (Summary)

• Start with wafer at current

step
• Add photoresist
• Pattern photoresist with
mask
• Step-specific etch, implant,
etc.
• Wash off resist

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 28

 Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor size
(and hence speed, cost, and power)
• Feature size f = distance between source and drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design rules
• Express rules in terms of  = f/2
– E.g.  = 0.3 m in 0.6 m process

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 29

 Design Rules
• Design rules govern the layout of individual
components: transistors, wires, contacts, vias
– How small can the gates be, and how small can the
wires be made?
• Conflicting Demands:
– component packing: more functionality, higher
speed
– Chip yield: smaller sizes can reduce yield (fraction of
good chips)
• Conservative vs aggressive design rules

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 30

 Foundry Interface
Layout
(mask set)

Designer Foundry

Design Rules
Process Parameters

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 31

 Geometric Design Rules

• Resolution
– Width and spacing of lines on one layer
• Alignment
– make sure interacting layers overlap (or don’t)
– Contact surround
– Poly overlap of diffusion
– Well surround of diffusion

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 32

 SCMOS Design Rules
• Scalable CMOS design rules
•
Feature size  = half the drawn gate
length (poly width)
• Mentor Graphics IC tool has built-in
design rule checker (DRC)
Example design rules:
Layer
Metal 1 Minimum Width
3
Separation 3
Metal 2
Poly 3 4
poly-poly: 2 
2 poly-diff: 1 
Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 33
 Simplified Design Rules
• Conservative rules to get you started

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 34

 Tub Ties and Latchup
• Substrate must be connected to power supply
• p-tub for nMOS to VSS (Gnd)
• N-tub for pMOS to VDD
• Connections made by special vias called tub ties
• Conservative design rule: place tub ties for every one or
two transistors
• Why not place one tie in each tub that has 50
transistors?

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 35

 Latchup
• Too few ties: high resistance between tub and power supply, leads
to parasitic bipolar transistors inhibiting normal chip operation
• Parasitic silicon-controlled rectifier (SCR)
• When both bipolar transistors are off, SCR conducts no current
• SCR turns on: high current short-circuit between VDD and Gnd.

V DD
VDD
Rnwell p-source
p+ n+ n+ p+ p+ n+
n-well
R nwell
Rpsubs n-source
p-substrate Rpsubs

(a) Origin of latchup (b) Equivalent circuit

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 36

 Gate Layout
• Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
• Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 37

 Inverter Layout
• Transistor dimensions specified as Width / Length
– Minimum size is 4 / 2 sometimes called 1 unit
– In f = 0.6 m process, this is 1.2 m wide, 0.6 m long

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 38

 Example: Inverter

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 39

 Example: NAND3
• Horizontal N-diffusion and p-diffusion strips
• Vertical polysilicon gates
• Metal1 VDD rail at top
• Metal1 GND rail at bottom
• 32  by 40 

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 40

 Stick Diagrams
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 41

 Stick Diagrams
• Designing complete layout in terms of rectangles can be
overwhelming
• Stick diagram: abstraction between transistor schematic and
layout
– Cartoon of a chip layout
• Replace rectangles by lines
VDD (blue)
p-type diffusion
VDD transistor
(yellow)

Metal 1 (blue)
a
a a Poly (red)
n-type
diffusion
Gnd (green) VSS (Gnd)

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 42

 Stick Diagram
VDD Metal 1
VDD

a b p-diffusion
a
z b
a

b
Poly
Gnd
n-diffusion

Metal 1 Gnd

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 43

 Wiring Tracks
• A wiring track is the space required for a wire
– 4  width, 4  spacing from neighbor = 8 
pitch
• Transistors also consume one wiring track

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 44

 Well spacing
• Wells must surround transistors by 6 
– Implies 12  between opposite transistor flavors
– Leaves room for one wire track

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 45

 Area Estimation
• Estimate area by counting wiring tracks
– Multiply by 8 to express in 

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 46

 Example: O3AI
• Sketch a stick diagram for O3AI and estimate area

– Y   A  B  C □D

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 47

 Example: O3AI
Y   A  B  C □D
• Sketch a stick diagram for O3AI and estimate area

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 48

 Example: O3AI
Y   A  B  C □D
• Sketch a stick diagram for O3AI and estimate area
–

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 49

 Some Layout Hints
• Plan the global structure • Wiring on orthogonal
(“big picture”), then metal layers
design cells – Assign preferred
– Floorplan directions to M1 and
– Wiring strategy M2
– Power and ground – Use diffusion only for
distribution devices, not for
– Systematic interconnect
placement – Use poly only for very
– Keep all pMOS/nMOS local interconnect
together
– Place transistors in rows:
share source/drain diffusion

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 50

 Cell Minimization
• Chip area (cell size) must be minimized carefully

Impact of die size/chip area on cost (unpackaged dies)

Nominal 1% increase 15% increase
Pentium die in die size in die size
Wafer cost $1,460 $1,460
Die size 160.2 mm2 $1,460
Die cost $84.06 $85.33
161.8 mm2 184.2$102.55
Chips 1% mm
increase
2 in die size leads to 3%
fabricated decrease in stock price for Intel!
per week 498.1 K 482.9 K 337.5 K
Added
annual cost $63.5 M $961 M
Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 51
Minimize number of diffusion strips
• How do we order the gate inputs (poly)?
• More diffusion strips → more spacing, more area
VDD Try a, b, c, d, e:
VDD
e
x x x x x
a
d

b c F
F

a
x x x x x x
b e
x a b c d
d e c Gnd
Two n-diff gaps, zero p-diff gaps
Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 52
 e b
VDD a
a

e d
d e c
a
d b c

b c
pMOS graph nMOS graph

a
b
d e c

Gnd

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 53

 • Euler path: Visit every edge exactly
once
• Find all Euler paths for nMOS and
pMOS graphs
• Find p- and n-path that have identical
labeling

• For example: d, e, a, b, c
• If no such path exists, then break diffusion
into strips

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 54

 e b
VDD pMOS graph
a a

e d
a d e c
d b c
b c
nMOS graph
VDD

a F x x x x
x
b
e c
F
d
Gnd

Ordering: d, e, a, b, c: x x x x x
Zero n-diff gaps, zero p-diff gaps e a b c
Gnd d

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 55

 Summary
• MOS Transistors are stack of gate, oxide, silicon
• Can be viewed as electrically controlled switches
• Build logic gates out of switches
• Draw masks to specify layout of transistors

• Now you know everything necessary to start

designing schematics and layout for a simple chip!

Mrs. Swetha B V, Assistant Professor VLSI Design(18EC62) 11/12/2024 56