Verilog for Sequential Circuits

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Defining a module
■ A module is the main building block in Verilog
■ We first need to declare:
 Name of the module
 Types of its connections (input, output)
 Names of its connections

a
Ve r i l o g
b y
Module
c

2
 a
Verilog
b y
Module
c

module example (a, b, c, y);

input a;
input b;
input c;
output
y;

// here comes
the circuit
description
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■ You can also define multi-bit busses.
 [ range_start : range_end ]

input [31:0 a; // a[31], a[30] .. a[0]

]
outpu [15:8 b1; // b1[15], b1[14] ..
t ] b1[8]
outpu [7:0] b2; // b2[7], b2[6] .. b1[0]
t
input clk
;

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Structural HDL Example
Short Instantiation
module top (A, SEL, C, Y);
input A, SEL, C;
output Y;
wire n1;

// alternative
small i_first ( A, SEL, n1 );

/* Shorter instantiation,
pin order very important */ module small (A, B, Y);
input A;
// any pin order, safer input B;
choice small i2 ( .B(C), output
.Y(Y), Y;
.A(n1) );
//
endmodule descriptio
n of small
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endmodule
Bitwise Operators
module gates(input [3:0] a, b,
output [3:0] y1, y2, y3, y4,
y5);

/* gates on 4two-input
Five different bi busse logic
*/
acting t s

assign y1 = b;a & // AND

assign y2 = b;a | // OR
assign y3 = b;a ^ // XOR
assign y4 = & ~(a // NAND
b);
assign y5 = ~(a | // NOR
b);
endmodul
e
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Conditional Assignment
■ ? : is also called a ternary operator because it operates on
3 inputs:
 s
 d1
 d0.

module [3:0] d0,

mux2(input d1,
input s,
outpu [3:0] y);
t
assign y = s ? d1 : d0;
// if (s) then y=d1 else
y=d0;

endmodule 7
 How to Express numbers ?
N’Bxx
8’b0000_0001

■ (N) Number of bits

 Expresses how many bits will be used to store the value

■ (B) Base
 Can be b (binary), h (hexadecimal), d (decimal), o (octal)

■ (xx) Number
 The value expressed in base, apart from numbers it can also have X and Z
as values.
 Underscore _ can be used to improve readability
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Verilog Number Representation
Verilog Stored Number Verilog Stored Number

4’b1001 1001 4’d5 0101

8’b1001 0000 1001 12’hFA3 1111 1001

0011
8’b0000_1001 0000 1001 8’o12 00 001 010

8’bxX0X1zZ1 XX0X 1ZZ1 4’h7 0111

‘b01 0000 .. 0001 12’h0 0000 0000

0000

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Precedence of Operations in Verilog
Highest ~ NOT
*, /, % mult, div, mod
+, - add,sub
<<, >> shift

<<<, >>> arithmetic shift

<, <=, >, >= comparison
==, != equal, not equal
&, ~& AND, NAND
^, ~^ XOR, XNOR
|, ~| OR, NOR
Lowest ?: ternary operator

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Sequential Logic in Verilog
■ Define blocks that have memory
 Flip-Flops, Latches, Finite State Machines

■ Sequential Logic is triggered by a ‘CLOCK’ event

 Latches are sensitive to level of the signal
 Flip-flops are sensitive to the transitioning of clock

■ Combinational constructs are not sufficient

 We need new constructs:
 always
 initial

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always Statement, Defining Processes
always @ (sensitivity
list) statement;

■ Whenever the event in the sensitivity list occurs, the

statement is executed

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Example: D Flip-Flop
module clk
flop(input ,
input [3:0] d,
outpu reg q);
t [3:0]
always @ (posedge
clk) q <= d; // pronounced “q gets
d”
endmodule

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Example: D Flip-Flop
module clk
flop(input ,
input [3:0] d,
outpu reg q);
t [3:0]
always @ (posedge
clk) q <= d; // pronounced “q gets
d”
endmodule
■ The posedge defines a rising edge (transition from 0 to 1).
■ This process will trigger only if the clk signal rises.
■ Once the clk signal rises: the value of d will be copied to q

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Example: D Flip-Flop
module clk
flop(input ,
input [3:0] d,
outpu reg q);
t [3:0]
always @ (posedge
clk) q <= d; // pronounced “q gets
d”
endmodule
■ ‘assign’ statement is not used within always block
■ The <= describes a ‘non-blocking’ assignment
 We will see the difference between ‘blocking assignment’ and
‘non-blocking’ assignment in a while

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Example: D Flip-Flop
module clk
flop(input ,
input [3:0] d,
outpu reg q);
t [3:0]
always @ (posedge
clk) q <= d; // pronounced “q gets
d”
endmodule
■ Assigned variables need to be declared as reg
■ The name reg does not necessarily mean that the value is
a register. (It could be, it does not have to be).
■ We will see examples later

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D Flip-Flop with Asynchronous Reset
module flop_ar clk,
(input reset
inpu ,
output
t reg q);
[3:0] d,
inpu
always @ (posedget clk, negedge reset)
begin
if (reset ‘0’) q <= 0; // when rese
== t
else q <= d; // when clk
end
endmodul
e

■ In this
examp
le: two
events
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can
D Flip-Flop with Asynchronous Reset
module flop_ar clk,
(input reset
inpu ,
output
t reg [3:0]
[3:0] d,
q);
inpu
always @ (posedget clk, negedge
reset)
if (reset == ‘0’) q <=
begin // when
els
0; q <= reset
e d; // when clk
end
endmodul
■e For longer statements a begin end pair can be used
 In this example it was not necessary

■ The always block is highlighted

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D Flip-Flop with Asynchronous Reset
module flop_ar clk,
(input reset
inpu ,
output
t reg [3:0]
[3:0] d,
q);
inpu
always @ (posedget clk, negedge reset)
begin
if (reset ‘0’) q <= 0; // when rese
== t
else q <= d; // when clk
end
endmodul
e

■ First
reset
is
checke
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d, if
D Flip-Flop with Synchronous Reset
module flop_sr clk,
(input reset
inpu ,
output
t reg [3:0]
[3:0] d,
q);
inpu
always @ (posedget clk)
begin
if (reset ‘0’) <= 0; // when rese
== q t
else q <= d; // when clk
end
endmodul
e

■ The
proces
s is
only
sensiti 21
D Flip-Flop with Enable and Reset
module flop_ar clk,
(input reset
inpu , en,
t [3:0] d,
inpu
output reg [3:0] q);
t
inpu clk. negedge
always @ (posedge
reset) t
if (reset == ‘0’) q <=
begin // when reset
0;
else if q <= // when en AND
(en) d; clk
end
endmodul
■e A flip-flop with enable and reset

 Note that the en signal is not in the sensitivity list

■ Only when “clk is rising” AND “en is 1” data is stored

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Example: D Latch
module latch clk
(input , [3:0]
input
output reg d,
[3:0]
q);
always @ (clk,
d) // latch is transparent
if (clk) q <= when
endmodul
d; // clock is 1
e

lat
[3:0] [3:0]
d[3:0] D[3:0] [3:0] [3:0]
Q[3:0] q[3:0]
clk C

q[3:0]

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Summary: Sequential Statements
■ Sequential statements are within an ‘always’ block
■ The sequential block is triggered with a change in the
sensitivity list
■ Signals assigned within an always must be declared as
reg

■ We use <= for (non-blocking) assignments and do not

use ‘assign’ within the always block.

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Why does an always Statement Memorize?
module comb inv,
(input [3:0]
input
output regdata,
[3:0]
result);
always @ (inv, // trigger with inv,
data) data
if (inv) result <= ~data;/ result is inverted
/ data
else result <= data; / result is data
endmodule /

■ This statement describes what happens to signal result

 When inv is 1, result is ~data
 When inv is not 1, result is data

■ Circuit is combinational (no memory)

 The output (result) is defined for all possible inputs (inv
data) 24
always Blocks for Combinational Circuits
■ If the statements define the signals completely, nothing is
memorized, block becomes combinational.
 Care must be taken, it is easy to make mistakes and unintentionally
describe memorizing elements (latches).

■ Always blocks allow powerful statements

 if .. then ..
 cas else
e
■ Use always blocks only if it makes your job easier

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Always Statement is not Always Practical…
reg [31:0] result;
wire [31:0] a, b,
comb; wire sel,

always @ (a, b, // trigger with a, b,

sel) sel
if (sel) result <= a; // result is a
else result <= b; // result is b
assign comb = sel ? a : b;

endmodule

■ Both statements describe the same multiplexer

■ In this case, the always block is more work

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The case Statement
■ Like if .. then .. else can only be used in
always blocks
■ The result is combinational only if the output is defined for
all cases
 Did we mention this before ?

■ Always use a default case to make sure you did

not forget a case (which would infer a latch)
■ Use casez statement to be able to check for don’t
cares
 See book page 202, example 4.28

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Non-blocking and Blocking Statements
Non-blocking Blocking
always @ (a) always @ (a)
begin begin
a <= 2’b01; a = 2’b01;
b <= a; // a is
// all assignments are made 2’b01 b =
here a;
// b is not (yet) 2’b01 // b is now
end 2’b01 as
well
■ Values are assigned at the ■ Value is assigned
end
end of the block. immediately.

■ All assignments are made ■ Process waits until the first

in parallel, process flow is assignment is complete, it
not-blocked. blocks progress.
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Why use (Non)-Blocking Statements
■ There are technical reasons why both are required
 It is out of the scope of this course to discuss these

■ Blocking statements allow sequential descriptions

 More like a programming language

■ If the sensitivity list is correct, blocks with non-blocking

statements will always evaluate to the same result
 It may require some additional iterations

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Example: Blocking Statements
■ Assume all inputs are initially ‘0’
always @ ( * )
begin
p = a ^ b ; // p = 0
g = a & b ; // g = 0
s = p ^ cin ; // s = 0
cout = g | (p & cout = 0
cin) ; //
end

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Example: Blocking Statements
■ Now a changes to
‘1’
always @ ( * )
begin
p = a ^ b ; // p = 1
g = a & b ; // g = 0
s = p ^ cin ; // s = 1
cout = g | (p & ; // cout = 0
cin)
end
■ The process triggers
■ All values are updated in order
■ At the end, s = 1

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Same Example: Non-Blocking Statements
■ Assume all inputs are initially ‘0’
always @ ( * )
begin
p <= a ^ b ; // p = 0
g <= a & b ; // g = 0
s <= p ^ cin ; // s = 0
cout <= g | (p & cout = 0
cin) ; //
end

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Same Example: Non-Blocking Statements
■ Now a changes to
‘1’
always @ ( * )
p
begin <= a ^ b ; // p = 1
g <= a & b ; // g = 0
s <= p ^ cin ; // s = 0
cout <= g | (p & ; // cout = 0
cin)
end
■ The process triggers
■ All assignments are concurrent
■ When s is being assigned, p is still 0, result is still
0
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Same Example: Non-Blocking Statements
■ After the first iteration p has changed to ‘1’ as well
always @ ( * )
begin
p <= a ^ b ; // p = 1
g <= a & b ; // g = 0
s <= p ^ cin ; // s = 1
cout <= g | (p & // cout = 0
cin) ;
end
■ Since there is a change in p, process triggers again
■ This time s is calculated with p=1

■ The result is correct after the second iteration

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Rules for Signal Assignment
■ Use always @(posedge clk) and non-blocking
assignments (<=) to model synchronous sequential logic
always @ (posedge clk)
q <= d; // nonblocking

■ Use continuous assignments (assign …)to model

simple combinational logic.
assign y = a & b;

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Rules for Signal Assignment (cont)
■ Use always @ (*) and blocking assignments (=) to
model more complicated combinational logic where the
always statement is helpful.

■ Do not make assignments to the same signal in more than

one always statement or continuous assignment
statement

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Finite State Machines (FSMs)
■ Each FSM consists of three separate parts:
 next state logic
 state register
 output logic

CLK
M next next k N
inputs state k state state output
outputs
logic
logic

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FSM Example: Divide by 3

S2

S0

S1

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FSM in Verilog, Definitions
module divideby3FSM (input clk,
input reset,
output q);

reg [1:0] state, nextstate;

parameter S0 =
2'b00; parameter S1
= 2'b01; parameter
S2 = 2'b10;

■ We define state
and nextstate as
2-bit reg

■ The parameter descriptions are optional, it makes reading

easier 39
FSM in Verilog, State Register
// state register
always @ (posedge clk, posedge reset)
if (reset) state <= S0;
else state <= nextstate;

■ This part defines the state register (memorizing process)

■ Sensitive to only clk, reset
■ In this example reset is active when ‘1’

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FSM in Verilog, Next State Calculation
// next state
logic
always @ (*)
S0 (state)
case nextstate =
: S1; nextstate
S1 = S2;
default:
: nextstate =
nextstate = S0;
endcase
S2 S0;
:
■ Based on the value of state we determine the value of
nextstate

■ An always .. case statement is used for

simplicity.

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FSM in Verilog, Output Assignments
// output logic
assign q = (state == S0);

■ In this example, output depends only on state

 Moore type FSM

■ We used a simple combinational assign

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FSM in Verilog, Whole Code
module divideby3FSM (input clk, input reset, output q);
reg [1:0] state, nextstate;

parameter S0 =
2'b00; parameter S1
= 2'b01; parameter
S2 = 2'b10;

always @ (posedge
clk, posedge reset)
// state register
if (reset) state
<= S0
S0; nextstate =
:
else S1; nextstate
S1 <=
state = S2;
:
default:
nextstate; nextstate
nextstate = =
S2@ (*) S0;
alwaysS0;
endcase
: // output
assign
// nextqstate
= (state
logic== S0); logic
endmodule
case (state)

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What Did We Learn?
■ Basics of Defining Sequential Circuits in Verilog
■ Always statement
 Is needed for defining memorizing elements (flip-flops, latches)
 Can also be used to define combinational circuits

■ Blocking vs Non-blocking statements

 = assigns the value immediately
 <= assigns the value at the end of the block

■ Writing FSMs
 Next state calculation
 Determining outputs
 State assignment
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