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Design of Sequential Circuits

Designing of Sequential Circuits

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nmdrafiqj2003
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21 views12 pages

Design of Sequential Circuits

Designing of Sequential Circuits

Uploaded by

nmdrafiqj2003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Design of sequential circuits

1-Bit inverting Register using pass transistor

Din Ф1 M1 Inv1 Q
1 1 ON 0 0 (Inverted Din)
1-Bit inverting Register using TG

Din Ф1 TG1 Inv1 Q


1 1 0 ON 0 0 (Inverted
Din)
1-Bit Non-inverting Register using Pass transistor

Din Ф1 Ф2 = M1 Inv1 M2 Inv2 Q


1 1 0 ON 0 OFF Retains the previous Retains the
stored value previous stored
value
0 0 1 OFF 0(Retains the ON 1 1 (Din)
previous stored
value)

• Whenever Ф1 = 0, Q gets the Data value i.e Din and when Ф1 = 1, Q retains the previous stored value of Din.
Sequential Logic
Sequencing elements
• Setup Time : Time required for the
data inputs must be valid before
the active transition of the clock.
• Hold Time : Time required for the
data inputs must remain valid after
the active transition of the clock.
• tpFF : Worst case Propagation
delay of the FF to produce the final
stable output. (Data input to be
passed on to Q).
Positive and Negative Latch based on multiplexers
Level sensitive Positive latch based on
multiplexer using NMOS pass transistor
Positive edge triggered register based on
master-slave configuration
Design of master-slave Flip-flop using
NMOS pass transistor

Inverting clocks (Overlapping) lead to the violation of setup


and hold time (Race condition) – Solution is to use two non-
overlapping clocks)
Generation of two phase non-overlapping
clocks

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