UNIT4: Basic Computer

Organization and Design

Topics
 Instructions Codes
 Computer Registers
 Computer Instructions
 Instruction Cycle
 Memory Reference Instructions
 Input Output and Interrupt
Instruction Codes
A process is controlled by a program
 A program is a set of instructions

that specify the operations, data, and

the control sequence
 An instruction is stored in binary code that

specifies a sequence of microoperations

 Instruction codes together with data are

stored in memory (Stored Program

Concept)
Program statements and
computer instructions

Computer instruction

Field specifying the Field specifying the

operation to be data To be operated
executed on
Instruction code format
 Instruction code format with two parts :
Op. Code + Address
 Op. Code : specify 16 possible operations(4 bits)
 Address : specify the address of an operand(12
bits)
 If an operation in an instruction code does not
need an operand from memory, the rest of the
bits in the instruction(address field) can be
used for other purpose
15 12 11 0 15 12 11
0

Op. Code Address data

instruction Not an instruction

 Number of Operands per
instruction
 No Operands HALT NOP

 1 operand NOT R4 R4  R4

 2 operands ADD R1, R2 R1  R1 + R2

 3 operands ADD R1, R2, R3 R1  R2 + R3

 > 3 operands ADD R4,R1,R2,R3 R4  R1+(R2*R3)

 Each specify one operation and 1,2, 3 or 4 data locations.

 Instructions are read from memory as
words

 Instructions can be formatted to fit in one or

more memory words.
 An instruction may contain
 An opcode + data (immediate operand)
 An opcode + the address of data (direct
addressing)
 An opcode + an address where the address of the data
is found (indirect addressing)
 Data only (location has no instructions)
 An opcode only (register-reference or input/output
instruction)
Direct address
Occurs When the Operand Part Contains the Address
of Needed Data.

1.Address part of IR is placed on the bus and loaded

back into the AR

2.Address is selected in memory and its Data placed on

the bus to be loaded into the Data Register to be used
for requested instructions
Direct address
Indirect address
Occurs When the Operand Contains the Address of the
Address of Needed Data.

1.Address part of IR is placed on the bus and loaded back

into the AR

2. Address is selected in memory and placed on the bus to

be
loaded Back into the AR

3. New Address is selected in memory and placed on the

bus
to be loaded into the DR to use later
Indirect address
Effective address:
• Effective address: Address where an
operand is physically located

Effective address: 457 Effective address: 1350

 Direct and Indirect addressing example

Addressing
Mode
5-2 Computer Registers
 Data Register(DR) : hold the operand(Data) read from memory

 Accumulator Register(AC) : general purpose processing register

 Instruction Register(IR) : hold the instruction read from

memory

 Temporary Register(TR) : hold a temporary data during

processing

 Address Register(AR) : hold a memory address, 12 bit width

5-2 Computer Registers
 Program Counter(PC) :
 hold the address of the next instruction to be read from
memory after the current instruction is executed
 Instruction words are read and executed in sequence
unless a branch instruction is encountered
 A branch instruction calls for a transfer to a
nonconsecutive instruction in the program
 The address part of a branch instruction is
transferred to
PC to become the address of the next
instruction
 To read instruction, memory read cycle is initiated, and
PC is incremented by one(next instruction fetch)
5-2 Computer Registers
 Input Register(INPR) : receive an 8-bit
character from an input device
 Output Register(OUTR) : hold an 8-
bit character for an output device
 5-2 Computer Registers

Register Number Register Register

symbol of bits name Function-----------------------
DR 16 Data register Holds memory operands
AR 12 Address register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction register Holds instruction code
PC 12 Program counter Holds address of instruction
TR 16 Temporary register Holds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character
Common Bus System
 The basic computer has eight registers, a
memory unit, and a control unit.

 Paths must be provided to transfer

information from one register to another and
between memory and registers

 A more efficient scheme for transferring

information in a system with many registers
is to use a common bus.
Mano’s Computer Figure 5-4 s0 s1 s2
Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
CLR
LD INR
DR 3
LD INR CLR

Adder E
& Logic
AC 4
CLR
LD INR
INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
Common Bus System
 The connection of the registers and memory of
the basic computer to a common bus system :

 The outputs of seven registers and memory are

connected
to the common bus
 The specific output is selected by mux(S0, S1, S2) :
 Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5),

TR(6)
 When LD(Load Input) is enable, the particular register

receives the data from the bus

 Control Input : LD, INC, CLR, Write, Read
Selection variables
 Selection variables: select a register or the
memory whose output is used as an input to
the common bus.

 To select one device out of 8, we need 3

select variables.
 For example, if S2S1S0 = 011, the output of
DR is selected as an output of the common
bus.
 Load input
Load input (LD): Enables the input of a
register to download bits form the
common bus. When LD = 1 for a
register, the data on the common bus is
read into the register during the next
clock pulse transition.

> Increment input (INR): Increments the content of a register.

> Clear input (CLR): Clear the content of a register to zero.
Incompatibility in register sizes

 • When the contents of AR or PC (12 bits) are

applied to the 16-bit common bus, the four
most significant bits are set to zero. When AR
or PC receives information from the bus, only
the 12 least significant bits are transferred to
the register.
12 least significant bits

12 bits
 Operations involve AC and DR Registers
Accumulator(AC) : s2
s1 Bus

Main Register Memo ry unit

4096×16 Address
s0
7

Microoperation : Wr i t e Read

clear AC, shift AC AR

1

LD INR CLR

PC 2
Data Register : ADD LD INR CLR

DR to AC, AND DR to DR
3

AC
LD INR CLR

Adder E
and AC 4
logic
LD INR CLR

3) INPR: Input device

INP R

IR 5

LD

TR
6
LD INR CLR

OUTR

Clock
LD

16-bit co mmo n bus

 CONTROL UNIT HARDWARE (Hardwired)
• Inputs to the control unit come from IR where an instruction is
stored.
• A hardwired control is implemented in the example computer using:
> A 3x8 decoder to decode opcode bits 12-14 into signals D0, ..., D7;

A flip-flop (I) to store the addressing mode bit in

IR
A 4-bit binary
sequence counter
(SC) to count
from 0 to 15 to
achieve time
sequencing;
>A 4x16 decoder
to decode the
output of the
counter into 16
timing signals,
T0, ..., T15
Instruction Cycle
 Fetch the instruction from memory
 Program counter (PC) holds the address of the
next instruction to be executed.
 PC incremented each time an instruction is
fetched.
 Decode the instruction
 Determines operation to be performed, addressing
mode and location of operands.
 Execute the instruction
5.5 Instruction Cycle
 A computer goes through the following
instruction cycle repeatedly:
do
1. Fetch an instruction from
memory
2. Decode the instruction
3.Read the effective address from
memory if the instruction has an
indirect address
4.Execute the instruction until a HALT
instruction is encountered
 Instruction Fetch
– Instruction Fetch : T0, T1

• T0 = 1
–1) Place the content of PC onto the bus by making the bus
selection inputs S2S1S0=010
–2) Transfer the content of the bus to AR by enabling the LD
input of AR
T0 : AR  PC Continue
indefinitely
T1 : IR  M [ AR], PC  PC unless
1 HALT
instruction is
encountered
– T1 = 1
• 1) Enable the read input memory
• 2) Place the content of memory onto the bus by making S2S1S0= 111
• 3) Transfer the content of the bus to IR by enable the LD input of IR
• 4) Increment PC by enabling the INR input of PC
 Instruction Cycle
 At T3, microoperations which take place
depend on the type of instruction. The four
different paths are symbolized as follows,

Control function Microoperation

D7`IT3: AR  M[AR], indirect memory transfer
D7`I`T3: Nothing, direct memory transfer
D7I`T3: Execute a register-reference
D7IT3: instruction
Execute an I/O
When D7`T3 = 1 (At T3 & IR(12-14)  111),instruction
the execution of memory-
reference instructions takes place with the next timing variable T4.
REGISTER-REFERENCE INSTRUCTIONS
•The 12 register-reference instructions are recognized by I = 0 and
D7 = 1 (IR(12-14) = 111). Each operation is designated by the
presence of 1 in one of the bits in IR(0-11). Therefore D7I`T3  r =
1 is common to all register-transfer instructions.
5.6 Memory Reference Instructions
• Opcode (000 - 110) or the decoded output Di (i = 0, ..., 6) are used
to select one memory-reference operation out of 7.
Memory Reference
Instructions
 Since the data stored in memory cannot be
processed directly (the memory unit is not
connected to the ALU), the actual execution
in the bus system require a sequence of
microoperations.

 (Note that T0-T2 for fetch an instruction; T3

for AR  M[AR] if indirect memory
addressing.
AND to AC
 AND to AC: Logical AND operation between AC and
the memory word specified by AR.
 (Note that T0-T2 for fetch an instruction; T3 for AR
 M[AR] if indirect memory addressing.

 Need 2 more cycles for the AND logical operation

since only DR is connected to ALU.)
 D0T4: DR  M[AR]
 D0T5: AC  AC ˆ DR, SC  0
 SC – start counter
ADD to AC
 ADD to AC: Arithmetic addition
operation between AC and the memory
word specified by AR.
 D1T4: DR  M[AR]
 D1T5: AC  AC + DR, SC  0
Load to AC
 LDA: Load to AC.
 (Need 2 cycles since AC input is not
connected to the bus.)

 D2T4: DR  M[AR]
 D2T5: AC  DR, SC  0
Store AC
 STA: Store AC.
 D3T4: M[AR]  AC, SC  0
5.7 IO and Interrupt
 Input-Output Configuration :

 Input Register(INPR), Output Register(OUTR)

 These two registers communicate with a

communication interface serially and with the
AC in parallel
 Each quantity of information has eight bits
of an alphanumeric code
 Timing and Control Signals

• The timing for all registers in the basic computer is controlled by a

master clock generator.
• The clock pulses are applied to all flip-flops and registers in the
system, including the flip-flops and registers in the control unit.
• The clock pulses do not change the state of a register unless the
register is enabled by a control signal.
• The control signals are generated in the control unit and provide
control inputs for the multiplexers in the common bus, control inputs in
processor registers, and micro-operations for the accumulator.
Components used by Timing and Control Signal
Structure
 Description:

• Control Unit is built of 3 components:

a) 2 Decoders
b) 1 Sequence Counter
c) Control logic gate
• 3 Opcode bits for decoding are passed to 3*8 Decoder (Output: D0-
D7)
• Sequence Counter 4*16 (4 inputs and 16 outputs) generates 16 bit
Timing Signals T0- T15, which separately triggers the Regsiters and
passed towards Control Logic gate to execute instructions segments
one by one at each time pulse.
How Components are connected:
 Description:

• Operands Address is passed towards C.L. gate

• 3 bits of Opcode (Coded form of operation example +) is passed
towards #*8 Decoder and 8 outputs D0- D7 are passed towards
C.L.Gate
• 16 Timing Signals T0- T15 are passed towards Control Logic gate
• Clear signal is used to clear the Sequence Counter
• Clock Pulses are applied by CLK signal
• INC increments the vale of Sequence Counter one by one
Timing signals and effects of Halt:
 Description:

• The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder.

The eight outputs of the decoder are designated by the symbols D0 through
D7.
• The subscripted decimal number is equivalent to the binary value of the
corresponding operation code. Bit 15 of the instruction is transferred to a flip-
flop designated by the symbol I.
• Bits 0 through 11 are applied to the control logic gates. The 4-bit sequence
counter can count in binary from 0 through 15.
• The outputs of the counter are decoded into 16 timing signals T0 through T15.
• The sequence counter SC can be incremented or cleared
synchronously. Most of the time, the counter is incremented to provide
the sequence of timing signals out of the 4 x 16 decoder.
• Once in a while, the counter is cleared to 0, causing the next active
timing signal to be T0.
• As an example, consider the case where SC is incremented to
provide timing signals T0, T1, T2, T3, and T4 in sequence.
• At time T4, SC is cleared to 0 if decoder output D3 is active. This is
expressed symbolically by the statement
• D3T4: SC <__ 0
• The timing diagram of Figure shows the time relationship of the
control signals.