ARITHMETIC CIRCUITS
Addition of Unsigned Numbers
The one-bit addition entails four possible combinations,
The sum bit s is the XOR function. The carry c is the AND function
of inputs x and y. A circuit realization of these functions is shown in
Fig. c. This circuit, which implements the addition of only two bits,
is called a half-adder.
Multibit Addition
for each bit position i, the addition operation may
include a carry-in from bit position i − 1.
This observation leads to the design of a logic circuit that
has three inputs xi , yi , and ci , and produces the two outputs
si and ci+1.
This circuit is known
as a full-adder.
Ripple-Carry Adder
For each bit position we can use a full-adder circuit,
connected as shown in Figure
• When the operands X and Y are applied as inputs to the adder, it
takes some time before the output sum, S, is valid. Each full-
adder introduces a certain delay before its si and ci+1 outputs
are valid. Let this delay be denoted as ∆t.
• Thus the carry-out from the first stage, c1, arrives at the second
stage ∆t after the application of the x0 and y0 inputs. The carry-
out from the second stage, c2, arrives at the third stage with a
2∆t delay, and so on.
• The signal cn−1 is valid after a delay of (n − 1) ∆t, which means
that the complete sum is available after a delay of n∆t. Because
of the way the carry signals “ripple” through the full-adder
stages, the circuit is called a ripple-carry adder.
Adder and Subtractor Unit
A XOR B
When Add/Sub = 0, it performs X + Y.
When Add/Sub = 1, it performs
X + Y’ + 1
= X + 2’s complement of Y
=X-Y
Multiplication
Two binary numbers can be multiplied using the same
method as we use for decimal numbers.
Arithmetic Comparison Circuits
Let A = a3a2a1a0 and B = b3b2b1b0. Define a set of
intermediate signals called i3, i2, i1, and i0. Each
signal, ik , is 1 if the bits of A and B with the same
index are equal.
That is, ik = (ak ⊕ bk)’ . The comparator’s AeqB
output is then given by AeqB = i3i2i1i0
Hierarchical Verilog Code
For larger designs, it is often convenient to create a
hierarchical structure in the Verilog code, in which there is
a top-level module that includes multiple instances of
lower-level modules.
Let n=4
module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;
fulladd stage0 (carryin, x0, y0, s0, c1);
fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);
endmodule
module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
assign s = x ∧ y ∧ Cin;
assign Cout = (x & y) | (x & Cin) | (y & Cin);
endmodule
• A Verilog module can be included as a subcircuit in
another module.
• The general form of a module instantiation
statement is given below.
module_name instance_name (.port_name ( [expression] )
{, .port_name ( [expression] )} );
The instance_name can be any legal Verilog identifier
and the port connections specify how the module is
connected to the rest of the circuit.
The same module can be instantiated multiple times in
a given design provided that each instance name is
unique.
Each port_name is the name of a port in the subcircuit,
and each expression specifies a connection to that
port.
Named port connections -The syntax .port_name is
provided so that the order of signals listed in the
instantiation statement does not have to be the same as
the order of the ports given in the module statement of
the subcircuit.
Ordered port connections-If the port connections are
given in the same order as in the subcircuit,
then .port_name is not needed.
Using Vectored Signals
Multibit signals are called vectors.
An example of an input vector is
input [3:0] W;
This statement defines W to be a four-bit vector. Its
individual bits can be referred to using an index value in
square brackets.
The most-significant bit (MSB) is referred to as W[3] and the
least-significant bit (LSB) is W[0].
input [0:3] W; Here W[0] is MSB and W[3] LSB
module adder4 (carryin, X, Y, S, carryout);
input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;
fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);
fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage3 (.Cout(carryout), .s(S[3]), .y(Y[3]), .x(X[3]), .Cin(C[3]));
endmodule
