BCSE205L - Computer Architecture and Organization
L T PC
3 0 03
Dr. M. Bhuvaneswari
Assistant Professor Senior Gr.2
School of Computer Science and Engineering
Vellore Institute of Technology, Vellore
[email protected]
Basic Processing Unit
ALU and Datapath
References:
Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer organization,
Mc Graw Hill, Fifth edition, Reprint 2011.
Computer Architecture organization – NPTEL – IIT Kharagpur
Fundamental Concepts
Phases of an Instruction Cycle
Fetch Cycle
Execution Cycle
Processor fetches one instruction at a time and
perform the operation specified.
Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
Processor keeps track of the address of the
memory location containing the next instruction to
be fetched using Program Counter (PC).
Instruction Register (IR)
Executing an Instruction
Fetch the contents of the memory location pointed to by
the PC. The contents of this location are loaded into the
IR (fetch phase).
IR ← [[PC]]
Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
Carry out the actions specified by the instruction in the
IR (execution phase).
The instruction decoder and control logic unit is
responsible for implementing the action specified by the
instruction loaded in the IR
Processor Organization
Internal
Internal processor
processor
bus
bus
Control
Control signals
signals
PC
PC
Instruction
Instruction
Address
Address decoder
decoderand
and
lines
lines
MAR
MAR control
control logic
logic
Single Bus
Memory
Memory
bus
bus
Organization of the
MDR
MDR
Data
Data
lines IR
IR
lines
YY Data path inside a
processor
Constant R0
R0
Constant 44
Select
Select MUX
MUX
Add
Add
AA BB
ALU Sub
Sub RRnn -- 11
ALU
control
control ALU
lines ALU
lines
Carry-in
Carry-in
XOR
XOR TEMP
TEMP
ZZ
Figure
Figure 7.1.
7.1. Single-bus
Single-bus organization
organization of
of the
the datapath
datapath inside
inside aa processor.
processor.
Executing an Instruction
An instruction can be executed by performing
one or more of the following operations in some
specified sequence.
Transfer a word of data from one processor
register to another or to the ALU.
Perform an arithmetic or a logic operation
and store the result in a processor register.
Fetch the contents of a given memory
location and load them into a processor
register.
Store a word of data from a processor register
into a given memory location.
Register Transfers
Internal processor
bus
Riin
Ri
The decoder generates the
Riout
control signals needed to
Yin select the registers involved
Y
and direct the transfer of
Constant 4 data.
Select MUX Registers + ALU +
A B interconnecting bus =
Datapath
ALU
Zin
Z out
Figure 7.2. Input and output gating for the registers in Figure 7.1.
Register Transfers
All operations and data transfers are controlled
by the processor clock.
Bus
Bus
00
D
D Q
Q
11
Q
Q
Ri
Riout
out
Ri
Riinin
Clock
Clock
Figure
Figure 7.3. Input and output gating for one register bit.
Figure7.3. Input and
7.3. Input andoutput
outputgating
gatingfor
forone
oneregister
registerbit.
bit.
Performing an Arithmetic or
Logic Operation
The ALU is a combinational circuit that has no
internal storage.
ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
What is the sequence of operations to add
the contents of register R1 to those of R2 and
store the result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
Fetching a Word from Memory
The response time of each memory access
varies (cache miss, memory-mapped I/O,…).
To accommodate this, the processor waits until
it receives an indication that the requested
operation has been completed (Memory-
Function-Completed, MFC).
Move (R1), R2
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]
Fetching a Word from Memory
Address into MAR; issue Read operation; data into MDR.
Memory-bus Internal processor
data lines MDRoutE MDRout bus
MDR
MDR inE MDRin
Figure 7.4.
Figure 7.4. Connection and control
Connection and controlsignals
signalsfor
forregister
registerMDR.
MDR.
Storing a word in memory
Execution of a Complete
Instruction
Add (R3), R1
Fetch the instruction
Fetch the first operand (the contents of the
memory location pointed to by R3)
Perform the addition
Load the result into R1
Execution of a Complete
Instruction Internal processor
bus
Add (R3), R1 Control signals
PC
Instruction
Address
decoder and
lines
MAR control logic
Memory
bus
MDR
Data
lines IR
Y
Constant 4 R0
Select MUX
Add
A B
ALU Sub R n - 1
control ALU
lines
Carry-in
XOR TEMP
Figure 7.1. Single-bus organization of the datapath inside a processor.
Execution of Branch
Instructions
A branch instruction replaces the contents of PC
with the branch target address, which is usually
obtained by adding an offset X given in the
branch instruction.
The offset X is usually the difference between
the branch target address and the address
immediately following the branch instruction.
Conditional branch
Execution of Branch
Instructions
Step Action
1 PCout , MAR in , Read, Select4, Add, Z in
2 Zout , PC in , Yin , WMF C
3 MDR out , IR in
4 Offset-field-of-IRout , Add, Z in
5 Z out , PCin , End
Figure 7.7. Control sequence for an unconditional branch instruction.
Multiple-Bus Organization
Bus A Bus B Bus C
Incrementer
PC
Register
file
Constant 4
MUX
A
ALU R
Instruction
decoder
IR
MDR
MAR
Memory bus Address
data lines lines
Figure 7.8. Three-b us organization of the datapath.
Multiple-Bus Organization
Add R4, R5, R6
Step Action
1 PCout , R=B, MAR in , Read, IncPC
2 WMFC
3 MDR outB , R=B, IR in
4 R4outA , R5outB , SelectA, Add, R6 in , End
Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,
for the three-bus organization in Figure 7.8.
Quiz Internal processor
bus
Control signals
What is the control PC
sequence for
Instruction
Address
decoder and
lines
MAR control logic
execution of the Memory
bus
instruction Data
lines
MDR
IR
Add R1, R2 Constant 4
Y
R0
including the Select MUX
instruction fetch Add
A B
phase? (Assume ALU Sub R n - 1
control ALU
lines
Carry-in
single bus XOR TEMP
architecture)
Z
Figure 7.1. Single-bus organization of the datapath inside a processor.
Hardwired Control Unit
Overview
To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.
Approaches required for generation of the
control signals.
Two categories:
Hardwired control unit design and
Microprogrammed control unit design
Hardwired system can operate at high speed;
but with little flexibility.
Control Sequences
Add (R3), R1
Hardwired control unit
• Here each step in this sequence is completed in
one clock cycle.
• Counter is used to keep track of the time step.
Hardwired control unit
The control signals are determined by the following
information.
Content of the control step counter.
Content of conditional flags.
Content of the instruction register.
External input signals such as MFC.
The encoder/decoder circuit is a combinational circuit –
Control Signal – Based on the inputs.
Step decoder provides separate signal line for each
step in the control sequence(T1,T2,...).
Depending upon maximum steps required for an
instruction, Step decoder is designed.
Hardwired control unit
For eg. If maximum of 10 steps are required,
then a 4X16 step decoder is used.
Output of the instruction decoder consists of a
separate line for each machine instruction.
Among the total set of instructions, the instruction
decoder selects one of them (means that
particular line will be set to 1 and others are 0).
For eg. If maximum of 100 instructions are
present in an architecture, then a 7X128
instruction decoder is used.
Hardwired control unit
Generation of Control Signals
How encoder generates Pcin and END?
How encoder generates Zin?
Zin = T1 + T6 • ADDM + T4 • BR + T5.ADDR…
This signal asserted at T1 for all instruction, during T6
for ADD instruction, during T4 for unconditional branch
and so on. Branch Add
T4 T6
T1
Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
Microprogrammed
Control Unit
Microprogrammed Control Unit Design
Control signals are generated by a program
similar to machine language programs.
The control store (CS) stores the micro
routines for all instructions of an ISA.
The sequence of steps corresponding to the
control sequence of a machine instruction is the
micro routine.
Each sequence of steps is a control word
(CW) whose individual bits represent the
various control signals.
Individual control words in a micro routine are
called microinstructions
Microprogrammed Control Unit Design
External
inputs
Starting and
branch address Condition
IR codes
generator
Clock PC
Control
store CW
Organization of the control unit to allow conditional branching in the microprogram.
Microprogrammed Control Unit Design
Step Action
1 PC out , MAR in , Read, Select4, Add, Zin
2 Zout , PC in , Yin , WMF C
3 MDR out , IR in
4 R3out , MAR in , Read
5 R1out , Yin , WMF C
6 MDR out , SelectY, Add, Zin
7 Zout , R1 in , End
Figure 7.6. Con trol sequence for execution of the instruction Add (R3),R1.
Microprogrammed Control Unit Design
MDRout
WMFC
MAR in
Select
PCout
R1out
R3out
Micro -
Read
PCin
R1 in
Z out
Add
End
IRin
Yin
instruction
Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
Figure 7.15 An example of microinstructions for Figure 7.6.
Microprogrammed Control Unit Design
Control Sequences
Control sequence for ADDR and Unconditional branch instruction.
Microprogrammed Control Unit Design
Horizontal Vs Vertical Microinstruction
Encoding
Diagonal Microinstruction Encoding
Horizontal Microinstruction Encoding
Horizontal Microinstruction Encoding
Vertical Microinstruction Encoding
Vertical Microinstruction Encoding
Diagonal Microinstruction Encoding
Diagonal Microinstruction Encoding
