Unit-1

Basics Of Digital Electronics:

Registers, Shift Registers, Introduction to combinational circuit,
Introduction to sequential circuits
Digital Electronics

 Binary digit is called a ‘Bit’

 Manipulation of binary information is done by Logic Circuits – Gates

 Input-Output relationship for gate is represented in tabular form – Truth Table

 One or many Inputs and One binary Output

A B Y=A.B A B Y=(A.B)’
0 0 0 0 0 1
0 1 0 0 1 1
1 0 0 1 0 1

1 1 1 1 1 0

A B Y=(A+B)’
A B Y=A+B 0 0 1
0 0 0 0 1 0
0 1 1 1 0 0
1 0 1 1 1 0

1 1 1
A B Y=AB’+A’
B
A Y=A’ 0 0 0
0 1 0 1 1
1 0 1
1 0
1 1 0

A B Y=A’B’+A
A Y=A B
0 0 0 0 1
1 1 0 1 0
1 0 0
1 1 1
Basic Identities of Boolean Algebra
 x+0=x  xy=yx

 x.0=0  x + ( y + z ) = ( x + y) + z

 x+1=1  x(yz)=(xy)z

 x.1=x  x(y+z)=xy+xz

 x+x=x  x + y x = ( x + y ) (x + z )

 x.x =x  ( x + y )’ = x’ y’

 x + x’ = 1
 ( x y )' = x’ + y’

 x . x' = 0
 ( x’ )’ = x
Draw Logic Diagram for the Expression
along with the Truth Table
 AB + A’C  ABC + ABC’ + A’C
De-Morgan Theorem

 F = AB + C’D’ + B’D = (A’ + B’) (C + D) (B + D’)

 Universal Gates

 Design NOT, OR and AND using NAND Gate  Design NOT, OR and AND using NOR Gate
Karnaugh Map (K-Map)

 ‘n’ variables will have ‘2n’ minterms



 Pair of 8, 4 and 2
Simplify Boolean Function

 F = BC +AC’

 F = C’ + AB’
Simplify Boolean Function
Sum of Product (SOP)

 F(A,B,C,D) = B’C’ + B’D’ + A’CD’

 Can you convert this SOP to POS form ?

Product of Sum (POS)

F( A ,B,C, D)=Σ(0 ,1,2,5 ,8,9,10)

Don’t Care Conditions
 Combinational Circuits

 Connected arrangement of Logic Gates with Input and Outputs

 Output depends only on the present input
 The combinational circuit do not use any memory.
 The previous state of input does not have any effect on the present state of the circuit.

‘n’ input ‘m’ output

variables Combinational Circuit
variables
Half Adder

 A combinational logic circuit with two inputs and two outputs.

 The half adder circuit add two single bit numbers
 This circuit has two outputs carry and sum.
 Full Adder (1-bit Adder)

 A combinational logic circuit with 3 inputs and 2 outputs.

 The Full adder circuit add 3 single bit Cary number
 This circuit has two outputs carry and sum.

ABC  ABC  ABC  ABC

A( BC  BC )  A( BC  BC )
A( B  C )  A( BC )
Sum = Let B  C  D
Carry = AD  AD
A D
A B C
 ABC  ABC  ABC  ABC
C ( AB  AB )  AB (C  C )
( A  B )C  AB

Cout=AB+BC+AC
 Full Adder using Half Adder

Full Adder

Sum= A⊕B⊕C
Carry=AB+(A⊕B)C

Half Adder

Sum= A⊕B
Carry=AB
The simplified expression of full adder carry

1. C = xy + yz + xz
2. C = xy
3. C = yz
4. C=x+y+z
The simplified expression of full adder carry

1. C = xy + yz + xz
2. C = xy
3. C = yz
4. C=x+y+z
Half Subtractor
Combinational circuit perform binary Subtraction
Accepts 2 input and Two output Difference and Borrow

D(A, B) = ∑m (1, 2)
Br(A, B) = ∑m (1)
Full Subtractor
Performs subtraction of 3 bits
This circuit has three inputs and two outputs.
The three inputs A, B and C, denote the minuend, subtrahend, and previous borrow, respectively.
The two outputs, D and Bout

Sum(A, B,C) = ∑m (1, 2, 4, 7)

Bout(A, B,C) = ∑m (1,2,3,7)
Bout = A’B’C + A’BC’ + A’BC + ABC
= C(AB + A’B’) + A’B(C + C’)
= C( A XNOR B) + A’B
= C (A XOR B)’ + A’B
Full Subtractor using Half Subtractor
Full Subtractor Half Subtractor

Diff= A⊕B⊕C Diff= A⊕B

Borr=A’B+(A⊕B)’C Borr=A’B

`
The difference bit output of a half subtractor is the same as

1. Difference bit output of full subtractor

2. Sum bit output of half adder
3. Sum bit output of full adder
4. Carry bit output of half adder
The difference bit output of a half subtractor is the same as

1. Difference bit output of full subtractor

2. Sum bit output of half adder
3. Sum bit output of full adder
4. Carry bit output of half adder
Design a 3 input digital circuit produces high output for two or more binary input high

A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Design a 3 input digital circuit produces high output for ODD decimal equivalent

A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Multiplexer
 A combinational circuit has maximum of 2n data inputs, ‘n’ selection lines and single output line.
 One of these data inputs will be connected to the output based on the values of selection lines
 It is a data selector device
 Size of multiplexer is :1

I0 0
Y =S’I0 + SI1
2:1 Multiplexer
I1 1

S
4:1 Multiplexer

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3
In a multiplexer, the selection of a particular input line is
controlled by ___________

1. Data controller
2. Selected lines
3. Logic gates
4. Both data controller and selected lines
In a multiplexer, the selection of a particular input line is
controlled by ___________

1. Data controller
2. Selected lines
3. Logic gates
4. Both data controller and selected lines
How many select lines would be required for an 8-line-to-1-line
multiplexer?

1. 2
2. 3
3. 4
4. 8
How many select lines would be required for an 8-line-to-1-line
multiplexer?

1. 2
2. 3
3. 4
4. 8
8:1 Multiplexer

S2 S1 S0 Out
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Out=S2’S1’S0’I0 + S2’S1’S0I1+ S2’S1S0’I2+ S2’S1S0I3

S2S1’S0’I4+ S2S1’S0I5+ S2S1S0’I6+ S2S1S0I7
De-Multiplexer
Switch one common input line to one of several output line based on select input - Data distributor
Size of demux 1: Example 1:4, 1:8, 1:16….. Demultiplexer

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
Most demultiplexers facilitate which type of conversion?

1. Decimal-to-hexadecimal
2. Single input, multiple outputs
3. AC to DC
4. Odd parity to even parity
Most demultiplexers facilitate which type of conversion?

1. Decimal-to-hexadecimal
2. Single input, multiple outputs
3. AC to DC
4. Odd parity to even parity
Why is a demultiplexer called a data distributor?

A. The input will be distributed to one of the outputs

B. One of the inputs will be selected for the output
C. The output will be distributed to one of the inputs
D. Single input to Single Output
Why is a demultiplexer called a data distributor?

A. The input will be distributed to one of the outputs

B. One of the inputs will be selected for the output
C. The output will be distributed to one of the inputs
D. Single input to Single Output
 Decoder
• A combinational circuit that has ‘n’ input lines and maximum of 2 n output lines.
• One of these outputs will be active High based on the combination of inputs present, when the decoder is
enabled.
• The outputs of the decoder are min terms of ‘n’ input variables lines when it is enabled
• Size of Decoder are 2:4, 3:8, 4:16….

A1 A0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0
 Full Adder using 3:8 Full Subtractor using 3:8
Decoder Decoder
S = A’B’C + A’BC’ + AB’C’ + ABC = Σ(1,2,4,7) DIFFERENCE = A’B’C + A’BC’ + AB’C’ + ABC = Σ(1,2,4,7)
CY = A’BC +AB’C +ABC’+ABC= Σ (3, 5, 6, 7) BORROW = A’B’C +A’BC’ +A’BC+ABC= Σ (1, 2, 3, 7)

Y
3:8 decoder using 2:4 decoder
Decoder with Enable
One of outputs will be ‘1’ when enable, E is ‘1’

A2 A1 A0 HIGH
OUTPUT
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
4:16 decoder A3 A2 A1 A0 HIGH
OUTPUT
0 0 0 0 Y0
Y0 0 0 0 1 Y1
0 0 1 0 Y2
A3 0 0 1 1 Y3
0 1 0 0 Y4
A2 0 1 0 1 Y5
0 1 1 0 Y6
A1
4:16 Decoder 0 1 1 1 Y7
1 0 0 0 Y8

A0 1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
Y15 1 1 0 1 Y13
1 1 1 0 Y14
EN
1 1 1 1 Y15
4:16 decoder using 3:8 decoder
A3 A2 A1 A0 HIGH
OUTPUT
0 0 0 0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13
1 1 1 0 Y14
1 1 1 1 Y15
4:16 decoder using 2:4 decoder A3 A2 A1 A0 HIGH
OUTPUT
0 0 0 0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13
1 1 1 0 Y14
1 1 1 1 Y15
Which of the following represents a number of
output lines for a decoder with 4 input lines?

A. 15
B. 16
C. 17
D. 18
Which of the following represents a number of
output lines for a decoder with 4 input lines?

A. 15
B. 16
C. 17
D. 18
4:2 Encoder
• A combinational circuit that has ‘2n’ input lines and maximum of ‘n’ output lines.

• Size of encoder are 4:2, 8:3, 16:4 …

 Introduction to Sequential Circuits
51

 Sequential circuits are those in which the output depends not only on the present inputs, but also on the previous output state
and/or the previous inputs.
 Difference between Combinational and
52 Sequential Circuits
Combinational Circuits Sequential Circuits
The output depends only upon the present inputs output depends not only on the present inputs, but also on the
previous output state and/or the previous inputs
No feedback Feedback available from output to input
No ability to store Ability to store
Easier to design, use and handle not easier to design, use and handle
No clock signal Clock signals are required for triggering purposes
Faster slower than combinational circuits
Elementary building block: Logic gates Elementary building block: Flip flops

Examples: Adder, Subtractor, Magnitude comparator, Examples: Latches, flip flops, counters, registers etc.
Multiplexer, Decoder, etc.
 QUICK QUIZ (POLL)
53

Which of the following is NOT the combinational circuit?

a) Magnitude Comparator
b) Multiplexer
c) Parity Generator circuit
d) Flip flop
 QUICK QUIZ (POLL)
54

Which of the following is NOT the combinational circuit?

a) Magnitude Comparator
b) Multiplexer
c) Parity Generator circuit
d) Flip flop
Flip Flop

 A Storage element employed in clocked Sequential Circuit – Flip Flop

 Flip Flop is a Binary cell capable for storing One Bit of Information
 Normally has two output (One Normal and other for Complement)
 F/F maintains a binary state until directed by a Clock pulse to switch States
SR Flip Flop
S R Q(t+1)
0 0 Q(t) No Change
0 1 0 Clear to 0
1 0 1 Set to 1
1 1 ? Indeterminate
 D (Data) Flip Flop
Slight modification of SR flip Flop – NOT Gate between S and R
D Q(t+1)
0 0 Clear to 0
1 1 Set to 1
 JK Flip Flop
Refinement of SR flip Flop – Overcome Indetermined Condition

J K Q(t+1)
0 0 Q(t) No Change
0 1 0 Clear to 0
1 0 1 Set to 1
1 1 Q’(t) Complement
 T (Toggle) Flip Flop
Modification of JK flip Flop – Shorting J and K

T Q(t+1)
0 Q(t) No Change
1 Q’(t) Complement
Edge Triggered

 State Change: Clock Pulse

 Rising Edge (Positive-edge Transition)
 Falling Edge (Negative-edge Transition)
 Setup Time (20ns)
 Minimum time that input must remain at constant value before the Transition
 Hold Time (5ns)
 Minimum time that input must not change after the positive Transition
 Propagation Delay (Max. 50ns)
 Time between the Clock input and the response in ‘Q’
Integrated Circuits

 An IC is a small silicon semiconductors crystal (Chip) containing the electronic components for
digital gates
 Various gates are interconnected inside chip to form required circuit
 Chip is mounted in ceramic/plastic container connected to external pin

 Small Scale Integration (SSI) : less than 10 gates

 Medium Scale Integration(MSI) : between 10 to 200 gates (decoders, adders, registers)
 Large Scale Integration(LSI) : between 200 and few thousands gates (Processors,
Memory Chips)
 Very Large Scale Integration (VLSI) : Thousands of gate within single package
(Large Memory Arrays, Complex Microcomputer Chips)