EMBEDDED & REAL TIME

SYSTEMS
 EMBEDDED & REAL TIME
SYSTEMS
Course Objective - In this course the student will learn about

 Embedded System design process using ARM Processor and its

applications

 ARM Architecture and Programming (Assembly and C)

 ARM interfacing with bus protocols

 Concepts and constraints related to real-time systems

 EMBEDDED & REAL TIME
SYSTEMS
Course Outcomes - After completing this course, student should be
able to

 Identify and summarize the characteristics and challenges of

designing an embedded system

 Utilize and apply ARM architecture for Embedded System Design

 Design simple input output hardware interfaces using ARM

 Explain the concepts and design requirements related to a real

time systems
 ERTS TEXT BOOKS/References
 1. Computers and Components: principles of embedded
computing system design, Wayne Wolf, Elseveir.
 2. Embedded System Design – A Unifies Hardware/Software
introduction - Frank Vahid, Tony D. Givargis, John Wiley,
2002.
 3. ARM Systems Developer’s Guides- Designing & Optimizing
System Software – Andrew N. Sloss, Dominic Symes, Chris
Wright, Elsevier
 4. An Embedded Software Primer, David E. Simon, Pearson
Education.
 5. ARM reference manual.
 Unit-1

Embedded Systems and its Applications:

 Embedded System Design Process
 Design challenge
 Applications of Embedded Systems
ARM Architectures:
• ARM Design Philosophy
• Registers, Program Status Register
• Instruction Pipeline
• Interrupts and Vector Table
• Architecture Revision
• ARM Processor Families
 embedded & Real Time systems
Definition
 An embedded system is a microprocessor- or
microcontroller-based system of hardware and
software designed to perform dedicated functions
within a larger mechanical or electrical system.

 Real time systems are those systems that work

within strict time constraints and provide a worst
case time estimate for critical situations.
Characteristics of embedded systems
 Single-functioned − An embedded system usually
performs a specialized operation and does the same
repeatedly.
 Tightly constrained − All computing systems have
constraints on design metrics, but those on an embedded
system can be especially tight.
 Design metrics is a measure of an implementation's
features such as its cost, size, power, and performance
 Reactive and Real time − Many embedded systems
must continually react to changes in the system's
environment and must compute certain results in real
time without any delay.
 Major steps in the embedded system design
process
Bottom-Up Design
Start with components to build a
system

Top-Down Design
Begin with the most abstract description
of the system and conclude with concrete
details
External constraints are one important source of difficulty in
embedded system design.
Some important problems that must be taken into account

 Hardware required

 Meeting deadlines

 Minimize power consumption

 Design for upgradability

 Work reliably – below issues further complicate the design process

REQUIREMENTS
REQUIREMENTS
 specification
 The specification serves as the contract between the
customer and the architects.

 The specification must be carefully written so that it

accurately reflects the customer’s requirements and
does so in a way that can be clearly followed during
design.
 specification of the GPS system
 A specification of the GPS system would include
several components:
 Data received from the GPS satellite constellation.
 Map data
 User interface.
 Operations that must be performed to satisfy customer
requests.
 Background actions required to keep the system running,
such as operating the GPS receiver
 Architecture Design
 The specification does not say how the system does
things, only what the system does.

 Describing how the system implements those

functions is the purpose of the architecture.

 The architecture is a plan for the overall structure of

the system that will be used later to design the
components that make up the architecture
Block diagram for the moving map.
Hardware architecture for the moving map.
software architectures for the moving
map.
 Designing Hardware and Software
Components
 The architectural description tells us what components
we need. The component design effort builds those
components in conformance to the architecture and
specification.

 The components will in general include both hardware—

FPGAs, boards and so on—and software modules.
 System Integration
 Only after the components are built do we have the
satisfaction of putting them together and seeing a
working system.

 Bugs are typically found during system integration,

and good planning can help us find the bugs quickly.
a) Consumer Electronics : cell phones, pagers, digital
cameras, camcorders, portable video games, calculators,
and personal digital assistants
Modern Applications – Cell Phones, PDAs and
Multimedia players
b) Home appliances -- microwave ovens, answering machines,
thermostat, home security, washing machines, smart TV's,
refrigerators and lighting systems
Modern Applications – Electric toothbrush
c) Office automation : fax d) Business equipment cash
machines, copiers, counting machines, alarm
printers and scanners systems, card readers,
product scanners, and
automated teller machines
Modern Applications – Robots
such as mars rovers
Modern Applications – Robots such
as mars rovers
 Modern Applications – Car Automation

Power Steering Power Windows Auto Lock Security Alarm

Car rear view camera

Air Bags

GPS
Cruise Control
Temperature Control

Transmission Control
 Real world Interfaces

Infrared light Sensors

Temperature Sensors

Vibration Sensors
Light Sensors

Capacitive Touch Sensors

Examples of embedded systems
 ARM
Advanced RISC Machines

Introduction and
Architecture
 ARM Applications

Apple iPod Nano Ford Sync In-Car Comm

&
Entertainment System

Nokia N93 Sony Playstation 3 (60GB)

ARM Partnership
ARM Advantage
 Why ARM ???
• ARM is one of the most licensed and thus widespread
processor cores in the world.

• Used especially in portable devices due to low power

consumption and reasonable performance

• Several interesting extensions available like Thumb

instruction set and Jazelle Java machine
 ARM History
• ARM – Acorn RISC Machine(1983–1985)
– Acorn Computers Limited, Cambridge,
England

• ARM – Advanced RISC Machine 1990

– ARM Limited, 1990
– ARM has been licensed to many
semiconductor manufacturers
 ARM History
• Key component of many 32 – bit embedded systems

• Portable Consumer devices

• ARM1 prototype in 1985

• One of the ARM’s most successful cores is the

ARM7TDMI,provides high code density and low
power consumption
 Advanced RISC Machines
• ARM Core uses Load/Store architecture

• ARM is Physical hardware design company.

• ARM licenses its cores out and other companies

make processors based on its cores
 RISC vs. CISC Architecture
RISC CISC
Fixed width instructions Variable length instructions
Few formats of instructions Several formats of
instructions
Load/Store Architecture Memory values can be used
as operands in instructions
Large Register bank Small Register Bank

Instructions are pipelinable Pipelining is Complex

 RISC vs. CISC Organization

RISC CISC
Hardwired instruction Microcode ROMS
decode instruction decoder
Single cycle execution of all Multi cycle execution on
instructions instruction
 RISC Advantages
• A Smaller Die Size

• A Shorter Development Time

• Higher Performance (Bit Tricky)

– Smaller things have higher natural frequencies
 RISC Disadvantages
• Generally poor code density (Fixed
Length Instruction)
 CISC vs. RISC
CISC RISC
Greater
Compiler Compile
Complexity
r

Code Code
Generation Generation

Greater
Processor Processor
Complexity
 Features used from RISC
• A Load/Store Architecture
• Fixed Length 32-bit Instructions
• 3- Address Instruction Formats
• Enhancements
• Auto increment & Auto Decrement Addressing
modes
• Multiple Load/Store
• Conditional Execution
 Load Store Architecture
• Memory can be accessed only through two dedicated
instructions
– LDR ; move word from memory to register
– STR ; move word from register to memory
• All other instructions have to work on registers only.
3 Address Instruction Format
f bits n bits n bits n bits
Function op 1 addr. op 2 addr. dest. addr.

Example

Add d, s1, s2 ; d =s1+s2

INTRODUCTION -ARM LPC2148 TDMI
 32 Microcontroller
 32 bit ALU
 32 bit Databus
 32 bit Address bus-Memory-4GB
 Von Neuman Architecture(Common memory for
program & data)
 3 stage pipeline(Fetch –Decode –Execute)
 Register bank(37 Registers)
 Load/store Architecture
 7 Operating modes
 ARM Design Policy
• Reduce power consumption
• High code density
• Price sensitive
• Reduce the area of the die taken up
by the embedded processor
• ARM Incorporatedhardware debug technology
Instruction set for Embedded Systems
• Variable cycle execution for
certain
instructions
•Inline barrel shifter to more
leading
complex instructions
•Thumb 16 – bit instructions
•Conditional execution
•Enhanced Instructions
Embedded System Hardware
 ARM Bus Technology
 Embedded devices use an on-chip bus that is internal
to the chip and that allows different peripheral
devices to be interconnected with an ARM core.

 There are two different classes of devices attached to

the bus.
• The ARM processor core is a bus
• Peripherals tend to be bus
• The Arm Advanced Microcontroller Bus
Architecture (AMBA) is an open-standard, on-chip
interconnect specification for the connection and
management of functional blocks in
system-on-a-chip (SoC) designs.
• It facilitates development of multi-processor
designs with large numbers of controllers and
components with a bus architecture
• Today, AMBA is widely used on a range of ASIC
and SoC parts including applications processors
used in modern portable mobile devices like
smartphones
• AHB is a bus protocol introduced in Advanced
Microcontroller Bus Architecture version 2
published by Arm Ltd company.

• large bus-widths (64/128/256/512/1024 bit).

 AMBA Bus ProtocoL
 A bus has two architecture levels. The first is a physical
level that covers the electrical characteristics and bus
width (16, 32, or 64 bits).
 The second level deals with protocol—the logical rules
that govern the communication between the processor
and a peripheral.
 The Advanced Microcontroller Bus Architecture
(AMBA) was introduced in 1996 and has been widely
adopted as the on-chip bus architecture used for ARM
processors.
Embedded System Software
 Embedded System Software
 An embedded system needs software to drive it.
 Each software component in the stack uses a higher
level of abstraction to separate the code from the
hardware device.

 The initialization code is the first code executed on

the board and is specific to a particular target or
group of targets. It sets up the minimum parts of the
board before handing control over to the operating
system
 Embedded System Software
 The operating system provides an infrastructure to
control applications and manage hardware system
resources.
 .The device drivers provide a consistent software
interface to the peripherals on the hardware device.
 Finally, an application performs one of the tasks required
for a device.
 The software components can run from ROM or RAM.
ROM code that is fixed on the device (for example, the
initialization code) is called firmware.
ARM Processor
Fundamentals
 ARM core dataflow model
Data
Instruction
Decoder
Sign Extend

Read

r15 Register File Rd

r0 – r15
pc Resu
A B lt
Rn Rm
A B Acc
Barrel Shifter

N MAC

ALU

Address Register

Incrementer
Address
 Registers
• ARM has Load Store Architecture

• General Purpose Registers can hold data or address

• Total of 37 Registers, each of 32 bit

• There are 17 or 18 active Registers

– 16 data registers
– 2 status registers
• There are up to 18 active registers: 16 data
registers and 2 processor status registers.
• The data registers are visible to the programmer
as r0 to r15.
• The ARM processor has three registers assigned
to a particular task or special function:
• r13, r14, and r15. They are frequently given
different labels to differentiate them from the
• other registers
 Registers – User Mode
• Registers R0 – R12 are General Purpose
Registers
• R13 is used as Stack Pointer (sp)
• R14 is used as Link register (lr)
• R15 is used as Program Counter (pc)
• CPSR is Current Program Status Register.
• SPSR is Saved Program Status Register
 Registers – User Mode
• Register r13 is traditionally used as the stack
pointer (sp) and stores the head of the stack in
the current processor mode.
• Register r14 is called the link register (lr) and is
where the core puts the return address
whenever it calls a subroutine.
• Registerr15 is the program counter (pc) and
contains the address of the next instruction
to be fetched by the processor.
 Registers – User Mode
• Depending upon the context, registers r13 and
r14 can also be used as general-purpose
registers, which can be particularly useful since
these registers are banked during a processor
mode change.
• However, it is dangerous to use r13 as a general
register when the processor is running any form
of operating system because operating systems
often assume that r13 always points to a valid
stack frame.
 Current Program Status Register
• The ARM core uses the cpsr to monitor and
control internal operations.
• The cpsr is a dedicated 32-bit register and resides
in the register file
• The cpsr is divided into four fields, each 8 bits
wide: flags, status, extension, and control.
• In current designs the extension and status fields
are reserved for future use.
• The control field contains the processor mode,
state, and interrupt mask bits. The flags field
contains the condition flags.
Current Program Status Register
 Interrupt Masks
• Interrupt masks are used to stop specific interrupt requests
from interrupting the processor.
• There are two interrupt request levels available on the ARM
processor core—interrupt request (IRQ) and fast interrupt
request (FIQ).
• The cpsr has two interrupt mask bits, 7 and 6 (or I and F),
which control the masking of IRQ and FIQ, respectively. The I
bit masks IRQ when set to binary 1, and similarly the F bit
masks FIQ when set to binary 1.
 Processor Modes
• The processor mode determines which registers
are active and the access rights to the cpsr register
itself.
• Each processor mode is either privileged or non
privileged
• A privileged mode: allows full read-write access to
the cpsr.
• Non privileged mode :only allows read access to
the control field in the cpsr but still allows read-
write access to the condition flags.
 Processor Modes
• Determines which registers are active and the
access rights to the cpsr register itself
• Privileged & Nonprivileged
– Abort
– Fast Interrupt Request
– Interrupt Request
– Privileged
Supervisor
– System
– Undefined
– User Nonprivileged
 Processor Modes
• Abort Mode: The processor enters abort mode
when there is a failed attempt to access memory
• Fast interrupt request and interrupt request
modes: correspond to the two interrupt levels
available on the ARM processor.
• Supervisor mode :is the mode that the processor
is in after reset and is generally the mode that
an operating system kernel operates in.
 Processor Modes
• System mode: is a special version of user mode
that allows full read-write access to the cpsr.
• Undefined mode: is used when the processor
encounters an instruction that is undefined or not
supported by the implementation.
• User mode: is used for programs and applications.
Banked Registers
 Banked Registers
• all 37 registers in the register file. Of those, 20
registers are hidden from a program at different
times.
• These registers are called banked registers and
are identified by the shading in the diagram.
 Changing mode on an exception
User Mode
r0
r1
• This change causes user
r2
r3
register r13 and r14 to be
r4
r5
banked
r6
r7
• The user registers are
r8
r9
replaced with registers
Interrupt
r10
r11
Request r13_irq and r14_irq
Mode
r12
r13 sp r13_irq
• spsr stores the previous
r14 lr
r15 pc
r14_irq
mode cpsr
cpsr
- spsr_irq
 Processor Mode
Mode Abbr: Privileged Mode[4:0]

Abort abt yes 10111

Fast Interrupt Request fiq yes 10001
Interrupt Request irq yes 10010
Supervisor svc yes 10011
System sys yes 11111
Undefined und yes 11011
User usr no 10000

cpsr is not copied into the spsr when a mode

change is forced due to a program writing
directly to the cpsr.
 Operation Modes
Mode Registers CPSR[4:0]
User User 10000
FIQ _fiq 10001
IRQ _irq 10010
Supervisor Mode _svc 10011
Abort _abt 10111
Undefined Instruction _und 11011
System User 11111
 Processor Modes
User Unprivileged mode for most applications to
run
FIQ Fast Interrupt Routine
IRQ Interrupt Routines
Supervisor Entered on reset and when there is a
exception
Abort Entered when data or instruction prefetch
aborted
Undefined When an undefined instructions is executed

System Privileged user mode for operating system

 State and Instruction Sets
• There are three instruction sets
– ARM
– Thumb
– Jazelle
The Jazelle instruction set is a closed instruction set and is
not openly available.

To take advantage of Jazelle extra software

has to be
licensed from both ARM Limited and Sun Microsystems.
 State and Instruction Sets
ARM Thumb
(cpsr T = 0) (cpsr T = 1)
Instruction Size 32 bit 16 bit

Core Instruction 58 30

Conditional Execution Most Only branch instructions

Data Processing Instructions Access to barrel shifter Separate barrel and ALU
and ALU instructions
Program Status Register R/W in privileged mode No direct access
Register Usage 15 GPR + PC 8 GPR + 7 high registers
+ PC
 State and Instruction Sets

Jazelle
(cpsr T = 0, J = 1)
Instruction Size 8 bit

Core Instruction Over 60% of the java bytecodes are implemented

in hardware; the rest of the codes are
implemented in software
 Condition Flags

• Condition flags are updated by comparisons and the

result of ALU operations that specify the S instruction
suffix. For example, if a SUBS subtract instruction
results in a register value of zero, then the Z flag in
the cpsr is set. This particular subtract instruction
specifically updates the cpsr.
 Condition Flags
Flag Flag Name Set when

Q Saturation The result causes an overflow and / or saturation

V oVerflow The result causes a signed overflow

C Carry The result causes an unsigned carry

Z Zero The result is zero, frequently used to indicate the

equality
N Negative Bit 31 of the result is a binary 1
 CPSR
Flags Status Extension Control
Fields
Bit 30 29 28 27 24 7 6 5 4 0

31

0 0 1 0 0 0 0 1 0 10011

Function nzCvq j i F t svc

cpsr = nzCvqjiFt_SVC
 CPSR
31 28 24 23 16 15 8 7 6 5 4 0
N Z C V J U n d e i n e d I F T mode
f
 hold information about the most recently performed ALU
operation
 set the processor operating mode

• Condition code flags

– N = Negative result from ALU • Interrupt Disable bits.
– Z = Zero result from ALU – I = 1: Disables the
IRQ.
– C = ALU operation Carried out
– V = ALU operation oVerflowed • T– Bit
F = 1: Disables the FIQ.

• J bit – Architecture xT only

– Architecture 5TEJ only – T = 0: Processor in ARM state
– J = 1: Processor in Jazelle – T = 1: Processor in Thumb
state • Modestate
bits
– Specify the processor mode
 Pipeline
• Is a mechanism a RISC processor uses to execute
instructions

• Using a pipeline speeds up execution by

fetching the next instruction while other
instructions are being decoded and executed
ARM7 Three stage pipeline
Fetch Decode
Execute

•Fetch loads an instruction from memory

•Decode identifies the instruction to be
executed
•Execute processes the instruction and
writes the result back to a register
 Pipelined instruction sequence
Fetch Decode Execute
Cycle 1
Time
Cycle 2 ADD
SUB ADD

Cycle 3 CMP SUB ADD

• Filling the pipeline

• Allows the core to execute an instruction
every cycle
 ARM9 Five stage pipeline
Fetch Decode Execute Memory
Write

•Higher operating frequency  higher

performance
•Latency increases
•Increase in instruction throughput by around
13% in 5 stage pipeline
•1.1 Dhrystone MIPS per MHz
 ARM9 Five stage pipeline
• Fetch
– The instruction is fetched from memory and placed in the instruction
pipeline
• Decode
– The instruction is decoded and register operands read from the
register file
• Execute
– An operand is shifted and the ALU result generated
• Memory (Buffer/Data)
– Data memory is accessed if required. Otherwise the ALU result is
buffered for one clock cycle to give the same pipeline flow for all
instructions
• Write (Write-Back)
– The results generated by the instruction are written back to the
register file, including any data loaded from memory
 ARM10 Six stage pipeline

Fetch Issue Decode Execute Memory

Write
• Increase in instruction throughput by
around 34% in 6 stage pipeline
• 1.3 Dhrystone MIPS per MHz
• Code written for the ARM7 will execute on ARM9 and
ARM10
 ARM Instruction Sequence
Fetch Decode Execute
cpsr
MSR IFt_SVC
Time Cycle 1
cpsr
Cycle 2 ADD MSR IFt_SVC
cpsr
Cycle 3 AND ADD MSR iFt_SVC

Cycle 4 SUB AND ADD

 Pipeline Characteristics
• An instruction in the execute stage will
complete even though an interrupt has been
raised

• The execution of a branch instruction or

branching by the direct modification of the
PC causes the ARM core to flush its pipeline
 ARM Exceptions
• ARM supports range of Interrupts, Traps,
Supervisor Calls, all grouped under
general heading of Exceptions
 Exceptions, Interrupts, and the Vector
Table
• When an exception or interrupt occurs, the processor
set the PC to a specific memory address
• The address is within a special address range called
the vector table
• The entries in the vector table are instructions that
branch to specific routines designed to handle a
particular exception or interrupt
• When an exception or interrupt occurs,the
processor suspends normal execution and
loading instructions from exception vector
starts
the table
 Vector Addresses
Exception / Interrupt Shorthand Address High Address

Reset RESET 0x00000000 0xffff0000

Undefined Instruction UNDEF 0x00000004 0xffff0004

Software Interrupt SWI 0x00000008 0xffff0008

Prefetch Abort PABT 0x0000000C 0xffff000C

Data Abort DABT 0x000000010 0xffff0010

Reserved - 0x000000014 0xffff0014
Interrupt Request IRQ 0x000000018 0xffff0018
Fast Interrupt Request FIQ 0x00000001C 0xffff001C
 Exceptions, Interrupts, and the Vector
Table

• Reset vector is the location of the first instruction executed by

the processor when power is applied. This instruction branches
to the initialization code.

• ■ Undefined instruction vector is used when the processor

cannot decode an instruction.

• ■ Software interrupt vector is called when you execute a SWI

instruction. The SWI instruction is frequently used as the
mechanism to invoke an operating system routine
 Exceptions, Interrupts, and the Vector
Table
• Prefetch abort vector occurs when the processor attempts to
fetch an instruction from an address without the correct access
permissions. The actual abort occurs in the decode
stage.

■ Data abort vector is similar to a prefetch abort but is raised

when an instruction attempts to access data memory without
the correct access permissions.

■ Interrupt request vector is used by external hardware to

interrupt the normal execution flow of the processor. It can only
be raised if IRQs are not masked in the cpsr.
 Exception Priorities
1. Reset (Highest Priority)
2. Data Abort
3. FIQ
4. IRQ
5. Prefetch Abort
6. SWI, Undefined
 Core Extensions
• Standard components placed next to the
ARM core
• Improve performance, manage resources,
provide extra functionality
• Three hardware extensions
– Caches
– Memory Management
– Coprocessors
 Caches

• Cache is a block of fast memory placed between main

memory and the core

• Cache provides an overall increase in performance

• ARM has two forms of cache

– Single unified cache for data and instruction
– Separate caches for data and instruction
 Memory Management
• MMU is a class of processor hardware
components for handling memory accesses
requested by the CPU.
• The functions of MMU’s are
– Translation of virtual address to physical
address.
– Memory protection
– Cache control etc
 Coprocessors
• Coprocessors can be attached to the ARM Processor

• A separate chip, that performs lot of calculations

for the microprocessor,relieving the CPU some of
its work and thus enhancing overall speed of
system.

• A secondary processor used to speed up operation

by taking over a specific part of main processors
work.

• The ARM processor uses coprocessor 15 registers to

control cache, TCMs, and memory management
 Description of cpsr
Parts Bits Architecture Description
Mode 4:0 all processor mode
T 5 ARMv4T Thumb state
I&F 7:6 all interrupt masks
J 24 ARMv5TEJ Jazelle state
Q 27 ARMv5TE condition flag
V 28 all condition flag
C 29 all condition flag
Z 30 all condition flag
N 31 all condition flag
 ARM processor families
• ARM7, ARM9, ARM10 and ARM11
• 7, 9, 10, 11 indicate different core
designs
 ARM family attribute comparison

ARM7 ARM9 ARM10 ARM11

Pipeline depth three-stage five-stage six-stage eight-stage
Typical MHz 80 150 260 335
mW/MHz 0.06 mW/MHz0.19 mW/MHz 0. 5 mW/MHz 0.4 mW/MHz
(+ cache) (+ cache) (+ cache)
MIPS/MHz 0.97 1.3 1.2
Architectur Von Neumann
1.1 Harvard Harvard
e 8 x 32
Harvard 8x 16 x 32 16 x 32
Multiplier 32
ARM Processor Families
 Architecture Revisions
Revision Example core ISA
enhancement
Implementation
ARMv1 ARM1 First ARM Processor
26 – bit addressing 32 – bit
ARMv2 multiplier
32 – bit coprocessor
ARMv2a ARM2 support
On chip cache
Atomic swap instruction
ARMv3 ARM6 & ARM7DI 32 – bit addressing
ARM3 Separate cpsr & spsr
New modes – UNDEF, ABORT
MMU support – virtual memory
ARMv3M ARM7M Signed & unsigned long
ARMv4 StrongARM multiply
Load – store instruction New
Mode - System
Revision Example core ISA enhancement
Implementation
ARMv1 ARM1 First ARM Processor
26 – bit addressing
ARMv2 ARM2 32 – bit multiplier
32 – bit coprocessor support
ARMv2a ARM3 On chip cache
Atomic swap instruction
ARMv3 ARM6 & ARM7DI 32 – bit addressing
Separate cpsr & spsr
New modes – UNDEF, ABORT
MMU support – virtual memory
ARMv3M ARM7M Signed & unsigned long multiply
ARMv4 StrongARM Load – store instruction
New Mode - System
 Instruction Set Architecture
Thumb
®
Architecture DSP Jazelle Media TrustZone Thumb-2
v4T *

v5TE * *

v5TEJ * * *

v6 * * * *

v6Z * * * * *
v6T2 * * * * *
 ARM Processors
• ARM7 Family  ARM11 Family
– ARM7EJ-S  ARM1136J-S
– ARM7TDMI  ARM1136JF-S
– ARM7TDMI-S  ARM1156T2(F)-
S
– ARM720T
 ARM1176JZ(F)-S
• ARM9/9E Families
 ARM11 MPCore
– ARM920T
– ARM922T  Cortex Family
– ARM926EJ-S  Cortex-A8
– ARM940T  Cortex-M1
– ARM946E-S  Cortex-M3
– ARM966E-S  Cortex-R4
– ARM968E-S
• Vector Floating Point  Other
Families Processors/Microarchitectures
– VFP10  StrongARM (DEC-Intel)
• ARM10 Family  Xscale (Intel- Marvell Tech)
– ARM1020E  Other
– ARM1022E
– ARM1026EJ-S
 Cortex Family
• ARM Cortex-A Series - Application processors
for complex OS and user applications
– ARM Cortex-A8, ARM Cortex-A9
• ARM Cortex-R Series - Embedded processors
for real-time systems
– ARM Cortex-R4(F)
• ARM Cortex-M Series – Embedded processors
optimized for cost sensitive applications, as
Mobile devices
– ARM Cortex-M0, ARM Cortex-M1, ARM
Cortex-M3
 Switching States
• ARM to Thumb
– Execute the BX instruction with state bit=1
• Thumb to ARM
– Execute the BX instruction with state bit=0
– An interrupt or exception occurs