AMBA PROTOCOL
By
ASHRITH S
Advanced Microcontroller Bus Architecture
• Introduced by ARM in 1996
• The AMBA is a open standard to connect and manage functional blocks in a System-on-chip (SoC).
• It facilitates development of multi-processor designers with large number of controllers and components
with a bus architecture.
• Today AMBA is used widely in ASIC and SoC parts and also applications processors used in modern
portable mobile devices like smartphones.
• Technology independent.
• Advanced cached CPU cores and the development of peripheral libraries.
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Evolution of AMBA
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Typical AMBA base Microcontroller
• High-performance system backbone bus (AMBA AHB or AMBA ASB), able to sustain the external memory
bandwidth, on which the CPU, on-chip memory and other Direct Memory Access(DMA) devices reside.
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Advanced Peripheral Bus(APB)
• APB is the bus interconnect used to connect one master to multiple slaves.
• Non pipelined protocol.
• AMBA 2 (APB 2) - Basically read and write operations.
• AMBA 3 (APB 1.0) - Wait state / ready state from slave.
• Error reporting from slave.
• AMBA 4(APB 2.0) – Transaction protection.
• Sparse data transfer.
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Advanced Peripheral Bus(APB)
APB Master
• Synchronous PRESETn and Clock(Global signals).
• One master and selection line based on number of slaves
• PADDR and PWDATA control signal to select address and write/read
operation.
• PREADY is signal from slave to master request.
• PSLVEER is slave error response for read or write operation by slave.
• Its doesn’t specify the kind of error occurred
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APB Slave
• There are multiple slave for a single master.
• Based on selection line the respective slave is selected .
• Control signal specify the address and write/read operation.
• PREADY is ready signal sent by slave when its free to serve the
master’s operation.
• Clock and reset are synchronise with master.
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Operating states
IDEL No transfer
PSELx= 0
PENABLE= 0
Transfer
PREADY=1 SETUP PSELx=1
But no transfer
PENABLE= 0
PREADY=1 and transfer
PREADY=0
ACCESS
PSELx = 1
PENABLE=1
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APB write transfer
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APB Read transfer
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Other signals in APB
• PSTRB - Enable spares data transfer on write data bus.
• PPROT – used to interconnect other devices in system to provide protection against illegal transaction.
• 3 bit wide
• PPROT[0] – ‘1’ for privileged transaction and ‘0’ for normal access.
• PPROT[1] – ‘1’ for non secure and ‘0’ for secure access.
• PPROT[2] – ‘1’ for instruction access and ‘0’ for data access.
Advantages
• Low bandwidth , low power and latched address.
Disadvantages
• Single master, performance suffers a bus load.
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Advanced High-performance Bus(AHB)
• High performance multiple master multiple slave bus architecture.
• Split transaction methodology.
• Shared bus system.
Bus Interconnect
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AHB Master
• Initiate read and write operation by providing
address and control information
• At a time only master allowed to use the bus.
• To transfer it require access grant from arbiter.
• Pipelined system where address phase and data
phase of different transactions overlapped.
• Address phase – information related to address,
direction, width of transfer.
• Data phase – It take one or more cycle if ready
is low from salve.
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AHB Slave
• Respond to read or write operation according to
master’s request.
• Respond to master about success, failure or wait
conditions from slave to communicate more
effectively.
• These response provided by slave using
HRESP[1:0] i.e., okay, error, retry/split.
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Arbiter
• Control on which master has access to bus at time
instance.
• Selection of active master on basis of prioritization
scheme (round robin or other selection method ).
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AHB Lite
• Lighter version of AHB.
• Only one master, so no need of arbiter.
• Transfer of data similar to AHB but no request or grant signal is required.
• Locked transfer can be done by HMASTLOCK.
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THANK YOU
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