Presentation on semi conductors and p-n Junction diode fabrication

Conductivity of SEMICONDUCTORS lies between that of conductors and insulators

Semiconductors:

II
Zn Cd hg

III
Al Ga In

IV
Si Ge Sn

V
P As Sb

VI
S Se Te

II-VI Compound Semiconductors: ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe

IV Elemental Semiconductors: Si, Ge

III-V Compound Semiconductors: AlP, AlAs, AlSb, GaP, GaAs, GaSb, InP, InAs, InSb Some other Semiconductors: SiC, AlN (Beta & Hexagonal), GaN (Beta & Hexagonal)

Why SILICON???
Pure Si has a relatively high electrical resistivity at room temperature. Electron Configuration:1s2 2s2p6 3s2p2 Electrons per Energy Level: 2,8,4
Shell Model

Si is most abundant element, comprises 25% of the earth's crust. Annual world production: e-grade 5000 & metallurgical grade: 480,000 tons; Austria, Italy, India, South Africa, Australia, Canada, USA, Brazil.

Properties of Silicon dioxide : (Si + O2 -----> SiO2 ) Density: 2.648 g/cc Melting point: 1600-1725 C Boiling point: 2230 C, 2503 K, 4046 F Solubility in water: 0.079 g /L thermal conductivity: 0.01 W/cm K

The PN Junction
Metallurgical Na Junction + + + + + + + +

Steady State
Nd + + + + + + + + + + + +

P ++

N- -

ionized acceptors + h+ drift +

Space Charge Region E-Field _ h+ diffusion e- diffusion _

ionized donors

When no external source is connected to the pn junction, diffusion and drift balance each other out for both the holes and electrons

= =

== e- drift

Space Charge Region: Also called the depletion region. This region includes the net positively and negatively charged regions. The space charge region does not have any free carriers. The width of the space charge region is denoted by W . Metallurgical Junction: The interface where the p- and n-type materials meet. Na & Nd: Represent the amount of negative and positive doping in number of carriers per centimeter cubed. Usually in the range of 1015 to 1020.

Fabrication of Silicon P-N Junction Diode

[Link] cleaning of silicon wafer 2. Oxidation 3. Photolithography [Link] oxide etching [Link] [Link] film Metal (Aluminum) Deposition [Link] [Link] Etching [Link]-Metal contact formation

SILICON WAFER CLEANING: (RCA PROCESS)

Removal of DUST / GREASE / SOLVENT: 1. Boil in TRICHLOROETHYLENE(TCE) for 3-5 min. followed by Ultra-Sonic agitation 2-3 minutes. 2. Boil in ACETONE ~ 3 min. followed by Ultra-Sonic agitation 2-3 minutes. 3. Boil in METHANOL ~ 3 min. followed by Ultra-Sonic agitation 2-3 minutes. 4. Wash in D.I Water. Removal of Native Oxide: 1. Dip in [Link]HF:H2O soln. for 10 sec. 2. Wash in D.I Water. Removal of HEAVY METAL IONS: 1. Dip in [Link]H2O:HCl:H2O2 and heat to ~ 80C 2. Wash in D.I Water for ~20 min.

 Silicon Oxidation:
The wafer cleaned as above is given following treatment to removal of Native Oxide prior to oxidation: 1. Dip in [Link]HF:H2O soln. for 10 sec. 2. Wash in D.I Water

OXIDATION CYCLE:
The oxidation furnace is set at a desired temperature say 1000oC and high purity oxygen is flown into its quartz tube. The wafer is loaded in the quartz boat of the oxidation tube and dried by hot flowing oxygen in the oxidation tube. The boat is pushed into the center of the furnace and following oxidation cycle is used to grow oxide on silicon surface. DRY--- WET --- DRY Oxidation Cycle The Grown Oxide Thickness is proportional to TEMPERATURE of oxidation, Water Bath Temperature and TIME of Oxidation.

 Photolithography:
The oxidized wafer is placed on the chuck of a spinner held there by vacuum. Few drops of positive photo-resist is spread over the wafer surface and the chuck is rotated at high speed (3000-6000 rpm) to obtain a uniform thin layer of photo-resist on the wafer surface. The thickness of photo-resist layer depends on viscosity and spin speed Pre-Bake: The coated wafer is put in a oven set at 90oC for 20 minutes. U. V Exposure: The pre-baked wafer is put on chuck of a Mask Aligner and an appropriate mask .It is then exposed to Ultra-Violet (U.V) light for a predetermined time approximately 2 minutes and 45 seconds. Development: After exposure, the wafer is developed in an appropriated time ~ 1 minute in the developer solution of the photo resist to dissolve soft (U. V exposed) photo-resist. Post-Bake: Developed wafer is then subjected to heat treatment in a oven at 120oC for 40 minutes

 OXIDE ETCHING Post-baked wafer is put in a polythene beaker containing Buffer HF (BHF) Solution to etch silicon oxide from the exposed region on the wafer. The wafer is kept in BHF for an appropriate time to completely etch out the oxide. Removal of Photo-resist: After oxide etching the water-cleaned wafer is boiled in ACETONE two times to completely remove the unexposed photo-resist from the wafer surface. The wafer is then rinsed in D.I water.

 DIFFUSION: It is a process in which semiconductor wafer is heated in presence of atoms of impurity element one intends to diffuse into the silicon. Impurity atoms do not get diffused in silicon dioxide. Thus SiO2 acts as mask for dopant-atoms. Therefore, when a wafer is subjected to diffusion after oxide etching, diffusion occurs only in the regions where no oxide exists or the areas from which oxide has been removed during etching. METAL DEPOSITION: A thin layer of aluminum is deposited on the shiny surface of the Si wafer.

PHOTOLITHOGRAPHY: Photolithography is required for device isolation many deices can be fabricated in a single wafer. It is done by the same process as stated earlier photolithography process.
ETCHING Aluminum etching is done on the selective portion. HARD PHOTO-RESIST REMOVAL: Hard photoresist is removed by acetone.

Pictorial representation of P-N Junction diode fabrication

Silicon dioxide

n-Silicon

Ultra Violet Rays

mask
Silicon dioxide

n-Silicon

Photo Resist Polymerization on U.V Exposure

Silicon dioxide

n-Silicon

Silicon Oxide ETCHING in BHF

Silicon dioxide

Boron atoms + Borosilicate glass

n-Silicon

Silicon dioxide

Impurity Deposition (Boron/Phosphorous) n-Silicon

Silicon dioxide p p

Photo Resist Aluminium

n-Silicon

U. V Rays
Glass Photoresist
Silicoon dioxide p p

Aluminium

n-Silicon

PHOTOLITHOGRAPHY FOR Metal Contacts

Silicon dioxide p

THIN METAL CONTACT

p

n-Silicon

After Photoresist Removal

Diodes chips are separated by scribing using a diamond point and packaged in a suitable package as shown in the figure.

Results:
Reverse Bias -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 -0.5 -0.2 0 6 7 8 9 10 -0.389 -0.116 -0.086 -0.06 -0.053 -0.04 -0.0215 -0.0133 -0.0075 -0.0039 -0.0027 -0.002 0 1.3 2.68 3.97 6.4 10.77 Forward Bias 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1 2 3 4 5 0.001 0.002 0.0035 0.005 0.0065 0.01 0.0124 0.0141 0.018 0.042 0.202 0.318 0.666

Voltage Current Voltage Current

Conclusion:
Fabrication of PN Junction is very costly as the apparatus involved are very costly but when produced in bulk it makes them affordable even for an ordinary man considering all off the making costs, a PN Junction diode is made in 3 paisa, which is sold in market for 50 paisa. Thus , PN Junction fabrication is done

References:
[Link]( professor dept. of electronics) [Link] [Link] eristics/Diode%[Link]

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