Hardware Description

Languages

Professor: Sci.D., Professor

Vazgen Melikyan

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Hardware Description Languages
Lecture - 1
1 Developed By: Vazgen Melikyan
Course Overview

 The Role and Classification of HDLs

 1 lecture
 System Verilog
 2 lectures
 SystemC
 3 lectures
 Verilog
 4 lectures
 VHDL
 3 lectures
 Process of Synthesis
 2 lectures

Synopsys University Courseware

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Hardware Description Languages
Lecture - 1
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2
The Role and Classification of
HDLs

Synopsys University Courseware

Copyright © 2014 Synopsys, Inc. All rights reserved.
Hardware Description Languages
Lecture - 1
3 Developed By: Vazgen Melikyan
Design Levels
Example of Mathematical
Level Modeling Object HDL
Modeling Object Apparatus

SystemVerilog,
System Structural Circuit RAM bus CPU Queuing theory
SystemC

Add
Accumulator
Functional
Register- Circuits on the Input
Transfer level of multibit Command Register
devices +1
Command Counter
Boolean Algebra Verilog,VHDL

Circuit on the
Gate level of gates and J
flip-flops
K

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Design Levels (2)
Example of Mathematical
Level Modeling Object HDL
Modeling Object Apparatus

System of
Circuit Electrical Circuit differential Spice
equations

n+
System of
p+ differential
Device IC Components n equations with
n+ partial
p derivative

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5
The Role of HDLs in Digital Design Flow
HDL Design .v, .vhd

VCS
-
HDL Simulation
.db constr.

DC/DCT
OK DFT, Power Compiler
Synthesis
DFT, Power .v, .sdf

Formality
- PrimeTime
Formal verific.
& STA Reports

OK ICC
Place & Route
DFT, Power, XTALK

A B C D E

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The Role of HDLs in Digital Design Flow (2)
A B C D E

.v, GDSII
- Parasitic STARRC
Extraction, STA, STARRC VX
SI PT, PTSI
Prime Rail
.sdf, .spef, RT VX, PT PX
OK timing-report

- Reports
Physical verification check Hercules

Fix violations OK
.sdb, .v, .vhd Reports
FAIL Gate level
Simulation VCS

PASS
RTL Design

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Hardware Description Languages
Lecture - 1
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7
HDL Usage in Digital Design Flow

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Hardware Description Languages
Lecture - 1 8
Developed By: Vazgen Melikyan
8
HDLs and Digital Standard Cell
Libraries
 To implement digital design Digital Standard
Cell Library (DSCL) is needed
 It contains HDL descriptions of each cell for
simulation and verification
 Cells from DSCL are instantiated in
synthesized gate-level HDL description

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Synopsys 32/28nm Digital Standard
Cell Library
 Uses 32/28nm EDK 1P9M 1.05V/2.5V design rules
 Aimed at optimizing the main characteristics of designed ICs
 Includes typical miscellaneous combinational and sequential logic cells for
different drive strengths
 Contains all the cells which are required for different styles of low power
(multi-voltage, multi-threshold, etc.) designs
 Isolation Cells, Level Shifters, Retention Flip-Flops, Clock Gating Cells, Always-on
Buffers and Power Gating Cells
 Provides the support of IC design with different core voltages to minimize
dynamic and leakage power
 Cell list compiled based on the analysis of different educational designs
 Contains 350 cells

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HDLs in DSCL Deliverables

N0 Type Description

1 .doc, .txt Databook / User guide, Layer usage file

2 .db, .lib Synthesis
3 .v Verilog simulation models
4 .vhd VHDL / Vital simulation models
5 .cdl, .sp LVS, HSPICE netlists

6 .spi Extracted C or/and RC netlists for different corners

7 .gds GDSII layout views

8 .lef LEF files
9 .fram, .cel Fram views, layout views and runset files

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11
Classification of HDLs

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 Synopsys University Courseware
Copyright © 2014 Synopsys, Inc. All rights reserved.
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Lecture - 1
Developed By: Vazgen Melikyan
13