CHAPTER 6

Interrupt and Interrupt

Service Routines

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• Introduction
- The process of data transfer between a MP and peripherals is controlled either by
a) microprocessor controlled ,or
b) Device (peripheral) controlled
- Peripheral controlled data transfer is employed when the peripheral is much
faster than the MP controlled scheme. E.g. DMA controlled data transfer.
- Generally, MP controlled data transfer is employed when the peripheral response
is slow relative to that the MP and when small amount of data are to be
transferred.
MP-controlled data transfer can take place under several conditions:-
i, unconditional - synchronous data transfer
ii, polling (status check) - S/W approach
iii, with READY signals - H/W approach
iv, with Handshake signals:- status check or interrupt Asynchronous data
v, Interrupt driven - H/W or S/W approach transfer

 Unconditional data transfer:- the MP assumes that the peripheral

is always ready and synchronized. The MP simply enables the port, transfers data,
and goes on to execute the next instruction. E.g. to display data at an LED port. 2
 Data transfer with Polling :- in this form of data transfer, the MP is kept in a loop to check
whether data are available. E.g. to read data from an input keyboard in a single-board
microcomputer, the MP can keep polling the port until a key is pressed.
 Data transfer with READY signal:- when peripheral response time is slower than the
execution time requirement of the MP, the READY signal can be used to add T-states, thus
extending the execution time. E.g. it is commonly used in a system with slow memory
chips.
 Data transfer with Handshake Signals:-in this case, signals are exchanged between the MP
and a peripheral prior to actual data transfer; these signals are called handshake signals.
E.g. between A/D and MP.

Handshake signals Data A/D

Data I/O . MP initiates a signal-start
Status . I/O indicates readiness -status
MP Port E/C
MP
Start Port S/C

Fig. Asynchronous data transfer Fig. Asynchronous data transfer

scheme for an A/D converter
. The MP sends a start of conversion signal, S/C to the A/D converter.
. The, A/D when conversion from analog to digital is over, makes end of
conversion signal, E/C high.
. The MP goes on checking E/C till it becomes high, and when E/C becomes
high, the MP issues instructions for data transfer. 3
 Data transfer with Interrupt driven:- when a peripheral
is ready to transfer data, it sends an interrupt signal to the
MP.
. The MP initiates an I/O device to get ready, and then it
executes its main program instead of remaining in a
program loop to check the status of the I/O device.
. When the I/O device becomes ready to transfer data, it
sends a high signal to the MP through a special input line
called an interrupt line.
. On receiving an interrupt the MP completes the current
instruction at hand, and then attends the I/O device.
- Interrupt driven data transfer is used for slow I/O devices.
- It is an efficient technique as compared to the other
asynchronous data transfer schemes. 4
Example:
. The MP sends first the start of
Conversion signal, S/C to the A/D
MP Data A/D
converter
E/C
INTR . Thereafter, the MP executes its main
Port S/C program
. When the A/D converter completes the
Fig. Interrupt driven data transfer task of conversion, it makes and end of
for an A/D converter conversion signal, E/C high.
. When the E/C signal ( which is
connected to INTR pin of the MP)
becomes high the MP is interrupted and
transfers data from A/D.
. After completing the data transfer the
MP returns back to execute the main
program.

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 Interrupt
Interrupt is a process where an external
device can get the attention of the
microprocessor.
The process starts from the I/O device
The process is asynchronous.
An interrupt is considered to be an emergency
signal that may be serviced.
The Microprocessor may respond to it as soon
as possible.
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• What happens when MP is interrupted ?
– When the Microprocessor receives an interrupt
signal, it suspends the currently executing
program and jumps to an Interrupt Service
Routine (ISR) to respond to the incoming
interrupt.
– Each interrupt will most probably have its own
ISR.
• The event that causes the interruption is called
Interrupt.

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 Interrupts in 8085
When the interrupt signal arrives:
 The processor will break its routine
 Go to a different routine (interrupt service routine)
 Complete the interrupt service routine(ISR)
 Go back to the “regular” routine
In order to execute an interrupt routine, the processor:
 Should be able to accept interrupts (interrupt enable)
 Save the last content of the program counter
 Know where to go in program memory to execute the ISR
 Tell the outside world that it is executing an interrupt
 Go back to the saved PC location when finished.
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• Interrupts increase processor system efficiency
by letting I/O device request CPU time only
when that device needs immediate attention.
• An interrupt is a subroutine call initialized by
external hardware.
• The request is asynchronous  it may occur at
any point in a program’s execution.

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 CLASSIFICATION OF INTERRUPTS
• Hardware Interrupt An interrupt caused by an “External signal”
• Software Interrupt An interrupt caused by “Special Instruction”
– Interrupts can be classified into two types:
• Maskable Interrupts (Can be delayed or Rejected)
• Non-Maskable Interrupts (Can not be delayed or Rejected)
– Interrupts can also be classified into:
• Vectored (the address of the service routine is hard-wired)
Where the subroutine starts is referred to as Vector Location
• Non-vectored (the address of the service routine needs to be supplied
externally by the device)

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Nonmaskable interrupt input
− The MPU is interrupted when a logic signal is applied
to this type of input.
Maskable interrupt input
− The MPU is interrupted ONLY if that particular input
is enabled.
− It is enabled or disabled under program control.
If disabled, an interrupt signal is ignored by the
MPU.

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 Response to Interrupt
There are two ways of redirecting the
execution to the ISR depending on whether the
interrupt is vectored or non-vectored.
Vectored: The address of the subroutine is
already known to the Microprocessor
Non Vectored: The device will have to
supply the address of the subroutine to the
Microprocessor

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8085 INTERRUPT STRUCTURE
• There are 5 interrupt inputs:
– TRAP (non-maskable)
– RST7.5
– RST6.5
– RST5.5
– INTR

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 8085 INTERRUPTS
• The ‘EI’ instruction is a one byte instruction and
is used to Enable the maskable interrupts.
• The ‘DI’ instruction is a one byte instruction and
is used to Disable the maskable interrupts.
• The 8085 has a single Non-Maskable interrupt.

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The 8085 has 5 interrupt inputs.
 The INTR input.
− The INTR input is the only non-vectored interrupt.
− INTR is maskable using the EI/DI instruction pair.
 RST 5.5, RST 6.5, RST 7.5 are all automatically
vectored.
− RST 5.5, RST 6.5, and RST 7.5 are all maskable.

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• TRAP is the only non-maskable interrupt in the 8085
• TRAP is also automatically vectored

Interrupt Name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

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8085 INTERRUPTS

TRAP
RST7.5
RST6.5
RST 5.5 8085
INTR
INTA

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There are four interrupt inputs in 8085 that transfer
the operation immediately to a specific address:
 TRAP : go to 0024
 RST 7.5: go to 003C
 RST 6.5 0034
 RST 5.5 002C
 RST 7.5, RST 6.5 and RST 5.5 are maskable
interrupts, they are acknowledged only if they
are not masked !
Vector Address = Interrupt number *
8
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• Finding the address of these vectored interrupts are very
easy. Just multiply 8 with the RST value i.e. for RST 7.5
the subroutine(ISR) address=8*7.5=60=(3C)H.
• For TRAP ,its RST value is 4.5,then the subroutine
address is 8*4.5=36=(24)H.
similarly you can calculate for other vector interrupt
addresses.
Vector
Interrupt Name Calculation
Address
INTR -- --
TRAP ( RST 4.5) 4.5x8=36 0024H
RST 5.5 5.5x8=44 002CH
RST 6.5 6.5x8=52 0034H
RST 7.5 7.5x8=60 003CH
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 Software Interrupt
• The 8085 recognizes 8 RESTART instructions:
RST n ( RST0 - RST7)
– Each of these would send the execution to a re-determined
hard-wired memory location:

Restart Instruction Vector Address

RST 0 CALL 0000H
RST 1 CALL 0008H
RST 2 CALL 0010H
RST 3 CALL 0018H
RST 4 CALL 0020H
RST 5 CALL 0028H
RST 6 CALL 0030H
RST 7 CALL 0038H

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 Priority Interrupts
In 8085 all interrupt line have been given a priority..
TRAP is the interrupt with the highest priority and INTR
is the lowest.
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR

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 Masking RST 5.5, RST 6.5 and RST 7.5
These three interrupts are masked at two levels:
 Through the Interrupt Enable flip flop and the
EI/DI instructions.
− The Interrupt Enable flip flop controls the
whole maskable interrupt process.
 Through individual mask flip flops that control
the availability of the individual interrupts.
− These flip flops control the interrupts
individually.
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 Maskable/Vectored Interrupt Process
1. The interrupt process should be enabled using the
EI instruction.
2. The 8085 checks for an interrupt during the
execution of every instruction.
3. If there is an interrupt, and if the interrupt is enabled
using the interrupt mask, the microprocessor will
complete the executing instruction, and reset the
interrupt flip flop.
4. The microprocessor then executes a call instruction
that sends the execution to the appropriate location
in the interrupt vector table.
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5. When the microprocessor executes the call
instruction, it saves the address of the next
instruction on the stack.
6. The microprocessor jumps to the specific service
routine.
7. The service routine must include the instruction
EI to re-enable the interrupt process.
8. At the end of the service routine, the RET
instruction returns the execution to where the
program was interrupted.

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The Interrupt Enable flip flop is manipulated
using the EI/DI instructions.
The individual masks for RST 5.5, RST 6.5 and
RST 7.5 are manipulated using the SIM
instruction (Set Interrupt Mask).
This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt mask
enabling and disabling the specific interrupts.

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SIM Instruction

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Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST
6.5 and bit 2 is the mask for RST 7.5.
− If the mask bit is 0, the interrupt is available.
− If the mask bit is 1, the interrupt is masked.
Bit 3 (Mask Set Enable - MSE) is an enable for setting the
mask.
− If it is set to 0 the mask is ignored and the old settings remain.
− If it is set to 1, the new setting are applied.
• Bit 4 of the accumulator in the SIM instruction allows
explicitly resetting the RST 7.5 memory even if the
microprocessor did not respond to it.
• Bit 5 is not used by the SIM instruction
• Bit 6 & Bit 7 is used for extra functionality such as serial
data transmission. 27
• Example: Set the interrupt masks so that RST5.5 is
enabled, RST6.5 is masked, and RST7.5 is enabled.
• First, determine the contents of the accumulator
- Enable 5.5 bit 0 = 0
- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0
- Allow setting the masks bit 3 = 1
- Don’t reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0 0 0 0 0 1 0 1 0
- Don’t use serial data bit 6 = 0
- Serial data is ignored bit 7 = 0 Contents of accumulator are: 0A H

EI ; Enable interrupts including INTR

MVI A, 0AH ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks

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 Exercise
1. Write instruction for
(a) masking RST 5.5 and unmasking RST 7.5 and RST 6.5
(b) mask all interrupt line
(c) unmasking all interrupt line

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 Non Vectored Interrupt
1. The interrupt process should be enabled using the EI
instruction.
2. The 8085 checks for an interrupt during the execution of
every instruction.
3. If INTR is high, MP completes current instruction,
disables the interrupt and sends INTA (Interrupt
acknowledge) signal to the device that interrupted .
4. INTA allows the I/O device to send a RST instruction
through data bus.
5. Upon receiving the INTA signal, MP saves the memory
location of the next instruction on the stack and the
program is transferred to ‘call’ location (ISR Call)
specified by the RST instruction. 30
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the
further interrupt within the program.
8. RET instruction at the end of the ISR allows the MP to
retrieve the return address from the stack and the
program is transferred back to where the program was
interrupted.
9. Although INTR is a maskable interrupt, it does NOT
need SIM to get enabled. Just instruction EI is enough.

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 Non-Vectored Interrupt
• The 8085 recognizes 8 RESTART instructions:
RST0 - RST7.
– Each of these would send the execution to a
predetermined hard-wired memory location:
Restart Instruction Equivalent to
RST0 CALL 0000H
RST1 CALL 0008H
RST2 CALL 0010H
RST3 CALL 0018H
RST4 CALL 0020H
RST5 CALL 0028H
RST6 CALL 0030H
RST7 CALL 0038H

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■ Pending Interrupts:
The 8085 has an instruction to sense pending interrupts.
The interrupts which are activated while a higher priority interrupt is in service.
- RIM is a 1-byte instruction.
- After executing this, we can get the status of interrupts in the accumulator as a
bit pattern .
- Each bit indicates a particular status.
- When this instruction is executed, the ACC is loaded with:
- pending interrupts
- the restart interrupt masks
- the contents of SID.
D7 D6 D5 D4 D3 D2 D1 D0
SID I 7.5 I 6.5 I 5.5 IE M7.5 M6.5 M5.5

interrupts Masks: 1= masked

status
Serial I/p data
bit, if any Interrupt enable flag: 1 = enabled

Pending interrupts: 1=pending

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