Embedded Software Design

Peter R. Wihl
(former Guest Lecturer)
 Overview
• Data flow practices (Throughput)
• Real time systems
• Software design overview
• Communication protocols
• An example software design

Feel free to ask questions at any time

 Execution Flow
• A diagram that describes the major steps in the
sequential software flow.
• Illustrates each logical step and decision point in
the overall design of the software.
• Provides a starting point for the design of the
software.
• Is to embedded software as logical architecture is
to hardware.
• Is mapped later to Routines, Functions or Objects
 Before Designing Execution Flow
1. Identify which logical architectural
modules are mapped to software.
2. Identify what time period all logical
software function must be completed in.
3. Identify any additional overhead
functionality due to modules mapped to
software and/or characteristics of the
physical design. ie. Polling/Interrupts
 Logical Design Architecture
Example
FS = 44.1 KHz

ADC
DRdy 16
Fr = 20 – 20 KHz
Vpp = 1 V Data_Ready
Voff = 0 V

ECC
Enable1 En 2
Controller Error
En
SM
Enable2
En Error 16
Enable3 Detect
DAC_Load ED_Enable

Load EnError
DAC
16 Correct
Fr = 20 – 20 KHz
Vpp = 1 V
Voff = 0 V
 Physical Architecture Mapping
FS = 44.1 KHz

ADC_Data[15:0]
ADC
DRdy 16
Fr = 20 – 20 KHz
Vpp = 1 V Data_Ready
Voff = 0 V ECC

Error

Microcontroller Error TP = 1/44.1 KHz

= 22.7 us
Detect
DAC_Load
Error
Correct
Load
DAC
16 DAC_Data[15:0]
Fr = 20 – 20 KHz
Vpp = 1 V
Voff = 0 V
 Logical Design Architecture
Example
FS = 44.1 KHz

ADC
DRdy 16
Fr = 20 – 20 KHz
Vpp = 1 V Data_Ready
Voff = 0 V

ECC
Enable1 En 2
Controller Error
En
SM
Enable2
En Error 16
Enable3 Detect
DAC_Load ED_Enable

Load EnError
DAC
16 Correct
Fr = 20 – 20 KHz
Vpp = 1 V
Voff = 0 V Mapped to microcontroller
 Role of Microcontroller
• Read 16-bit word from ADC
• Calculate Error Correction Code (2-bit)
• Inject possible error
• Detect if there is an error
• If there is an error correct it
• Write new 16-bit word to DAC
 Execution Flow Diagram
Initialize Calculate if there
is error
Calculate ECC

Error
Detected?
Read ADC Byte
(Register)

Store ECC Value

Calculate correct
ADC word value
Write ADC Byte to
memory

Inject possible
error Write Byte to DAC

Last byte in No
word?

Yes
Last byte in No
word?

Yes
 Data Throughput in SW
• What is synchronous data flow?
– Data arrives at regular intervals
• What is asynchronous data flow?
– Data does not arrive at regular intervals
• What is isochronous data flow?
– Data must be delivered within certain time
constraints
 Data Flow Practices
• Polling
• Interrupt triggered (blocking)
• Interrupt triggered (non-blocking)
• Event driven
– Often referred to as interrupt driven
 Sample Problem
• Need to receive 16 bytes into a buffer and
then process the buffer
• Bytes arrive asynchronously
Polling Overview
Enter Loop

Read ADC Port

Store ADC Value

No
Buffer Full?

Yes

Process Buffer
 Polling
main
do forever
count = 0
while count < 16
while byte not ready
nop
get byte
buffer[count] = byte
incr count
process buffer
Interrupt (Blocking) Overview
IRQ Loop

Enter IRQ
Main Loop

Disable Interrupts Enter Main

Read ADC Port

Enable Interrupts

Store ADC Value

No Loop Forever
Buffer Full?

Yes

Process Buffer

Enable Interrupts

Exit IRQ
 Interrupt Triggered
(Blocking)
interrupt rx_byte main
disable interrupts enable interrupts
count = 0 do forever
while count < 16 nop
get byte
buffer[count] = byte
incr count
process buffer
enable interrupts
return
Interrupt (Non-Blocking) Overview
IRQ Loop
Main Loop
Enter IRQ
Enter Main

Yes
Buffer Full?

No
Enable Interrupts

Read ADC Port

Process Buffer

Count = 0
Store ADC Value

Increment Count

Increment Count

Loop Forever

Exit IRQ
 Interrupt Triggered
(Non-blocking)
interrupt rx_byte main
if count < 16 count = 0
get byte enable interrupts
buffer[count] = byte do forever
incr count nop
else if count = 16
process buffer
count = 0
return
Event Driven Overview
IRQ Loop Main Loop

Enter IRQ Enter Main

No Count = 0
Count <16

Yes

Enable Interrupts

Read ADC Port

Process = 1

Store ADC Value

Process Buffer

Increment Count

Process = 0

Exit IRQ
 Event Driven
interrupt rx_byte main
if count < 16 count = 0
get byte enable interrupts
buffer[count] = byte do forever
incr count if count = 16
return process buffer
count = 0
 Real Time
• Hard real time
– Absolute deterministic response to an
event
• Soft real time
– Average response to an event
Embedded Software Practices

Peter R. Wihl
ECE 164 Spring 2004
 Overview
• Data flow practices
• Real time systems
• Communication protocols
• Software design overview
• An example software design

Feel free to ask questions at any time

 Data Flow Types
• What is synchronous data flow?
• What is asynchronous data flow?
• What is isochronous data flow?
 Data Flow Types
• What is synchronous data flow?
– Data arrives at regular intervals
• What is asynchronous data flow?
– Data does not arrive at regular intervals
• What is isochronous data flow?
– Data must be delivered within certain time
constraints
 Data Flow Practices
• Polling
• Interrupt triggered (blocking)
• Interrupt triggered (non-blocking)
• Event driven
– Often referred to as interrupt driven
 Sample Problem
• Need to receive 16 bytes into a buffer and
then process the buffer
• Bytes arrive asynchronously
 Polling
main
do forever
count = 0
while count < 16
while byte not ready
nop
get byte
buffer[count] = byte
incr count
process buffer
 Interrupt Triggered
(Blocking)
interrupt rx_byte main
disable interrupts enable interrupts
count = 0 do forever
while count < 16 nop
get byte
buffer[count] = byte
incr count
process buffer
enable interrupts
return
 Interrupt Triggered
(Non-blocking)
interrupt rx_byte main
if count < 16 count = 0
get byte enable interrupts
buffer[count] = byte do forever
incr count nop
else if count = 16
process buffer
count = 0
return
 Event Driven
interrupt rx_byte main
if count < 16 count = 0
get byte enable interrupts
buffer[count] = byte do forever
incr count if count = 16
return process buffer
count = 0
 Real Time
• Hard real time
– Absolute deterministic response to an
event
• Soft real time
– Average response to an event
 Trick Questions
• Which is better, hard or soft real time?
• Which design methods are hard real time?
• Which design methods are soft real time?
 Communication Protocols
• What is a communication protocol?
– An established set of conventions by which
multiple systems exchange data
• The speech analogy
– The sounds you can make are the
communication medium
– The language you use is the protocol
 Sample Protocol
Byte Data
0 Synchronization
1 Payload size
2…2+size Payload
2+size+1 Packet checksum
 Protocol Interrupt
interrupt rx_byte
get byte PAYLOAD
checksum = byte ⊕ checksum buffer[count] = byte
switch (state) incr count
SYNC if count = size
if byte = sync state = CHECKSUM
checksum = byte CHECKSUM
state = SIZE if checksum = 0
SIZE state = ACCEPT
size = byte else
if size > 0 state = SYNC
count = 0 ACCEPT
state = PAYLOAD drop byte
else return
state = CHECKSUM
 Protocol Main
main • This is a simple event
state = SYNC
enable interrupts loop that provides
do forever mutual exclusion for
if state = ACCEPT the buffer
process buffer
state = SYNC
Time For A Break
 Software Design Overview
• Requirements Analysis
• Architecture
• Design
• Implementation
• Module Testing
• Design Validation Testing
 Example Problem
• I want to build a Heads Up Display for my
car.
• I would like to see both my engine RPM
and fuel economy on my windshield.
• My car has a serial diagnostic interface that
provides this data.
 Requirements
• System shall have a Heads Up Display
(HUD)
• System shall interface with vehicle’s
onboard diagnostic system
• HUD shall display current RPM
• HUD shall display current fuel economy
(MPG)
 Hardware Constraints
• Vehicle’s onboard diagnostic system
– Needs a wake-up signal sent every 1 second
– Operates at 10,500 bps
• Heads Up Display
– 256x128 pixels
– Full display must be calculated and mirrored
– Operates at 115,200 bps
 Processor Requirements
• Processor shall have 2 UARTs
1. Vehicle’s onboard diagnostic system
2. Heads Up Display
• Processor shall have a timer
– Vehicle’s onboard diagnostic system wake-up
• Processor shall have more than 8192 bytes of
memory
– Processed display image (4096 bytes)
– Mirrored display image (4096 bytes)
Hardware Design
Vehicle
data

Serial vehicle data

Processor /
microcontroller

Serial display control

Heads Up
Display
 Software Architecture
Vehicle Vehicle data
Serial vehicle data
data interface

RPM data MPG data

RPM data MPG data

formatting formatting

RPM text MPG text

Display processing

Display image

Display control Heads Up

Serial display control
interface Display
 Software Design
• Modules
– Vehicle Diagnostic Interface (VDI)
– RPM Data Formatting (RDF)
– MPG Data Formatting (MPG)
– Display Processing (DP)
– Display Control Interface (DCI)
 Software Design
• Modules
– Vehicle Diagnostic Interface (VDI)
– RPM Data Formatting (RDF)
– MPG Data Formatting (MPG)
– Display Processing (DP)
– Display Control Interface (DCI)
• Main/Initialization
Vehicle Diagnostic Interface
Serial vehicle data Serial vehicle data

Send wake up
Receive block Timer
signal

Data block

Data type?

RPM MPG

Extract RPM data Extract MPG data

RPM data MPG data

 Vehicle Diagnostic Interface
interrupt rx_byte main
… …
rx_state = ACCEPT do forever
… …
return
if rx_state = ACCEPT
extract_data
extract_data
if data type = RPM rx_state = SYNC
extract RPM data …
rpm_format(data)
else if data type = MPG
extract MPG data
mpg_format(data)
return
 Vehicle Diagnostic Interface
interrupt timer main
wakeup = 1 …
return do forever
…
tx_wakeup if wakeup = 1
send wakeup control tx_wakeup
block wakeup = 0
return …
RPM Data Formatting
RPM integer data

Integer to text
conversion

Text RPM value

Text formatting

Formatted RPM text

MPG Data Formatting
MPG integer data

Integer to floating
point conversion

Floating point MPG value

Floating point to
text conversion

Text MPG value

Text formatting

Formatted MPG text

Display Processing
Formatted RPM text Formatted MPG text

RPM image MPG image

generation generation

RPM image MPG image

RPM placement MPG placement

Placed RPM Placed MPG

Display image
generation

Display image

Mirror image

Mirrored display image

Display Control Interface
Mirrored display image

Image to
command
conversion

Display command

Command send

Serial display control

 Test Plan
1. Test functionality of every module
2. Test functionality of every module
interaction
3. Test functionality of the final system
 Implementation

This is when you actually write your code.

 Module Testing
• Simple implementations to test a single
module or module interaction
• Total testing code will often be larger than
the actual system’s code base
• Is this good or bad?
 Design Verification Testing
• A scripted test plan that guides a tester
through use of the system
• A table with the following:
– Every system requirement
– Whether or not the requirement was met