Outline
Introduction
Abstract
Cache Coherence mechanisms
Protocols for multi-core system architectures
Challenges in cache coherency
Conclusion
Introduction: Cache Coherency
the ability of multiprocessor system cores to share the same
memory structure while maintaining their separate instruction
caches.
used in coherence protocols to maintain data consistency
between cache memory in multiprocessor systems.
Various hardware and software-based cache coherent
mechanisms including contemporary protocols, have been
thoroughly explored.
Cache coherency addressed
in multi-core system
architecture
Introduction: Cache Coherency
Cache coherency addressed in multi-core system
architecture
Introduction: Cache Coherency
Cache coherency
addressed in
shared memory
architecture
Abstract
focuses on analyzing the different cache coherence techniques
used in SoC devices.
With a variety of cache coherence techniques to choose from,
the best strategy is determined by a number of factors such as
latency, scalability and so on.
The objective is to explore cache coherence protocols and
their challenges for multi-core systems.
Cache coherence mechanisms
Organization of cache coherence
Average memory access time
𝑇 𝑎𝑣𝑔 =𝑇 𝐻 +𝑇 𝑀 .𝑇 𝑃
Partitioning memory locations into iterations or epochs
Cache coherence mechanisms
1. Distributed memory 2. Asymmetric multiprocessing architecture
architecture
3. Maintaining cache coherence
4. Directory based cache coherence
5. Snooping cache coherence
Protocols for multi-core system
architectures
1. MSI Protocol : identifies the situations in which a cache line might be
modified (M)
2. MESI Protocol : extension of MSI protocol in that there are two transitions for
each write operation, even if the data block is not shared
3. MOSI Protocol : Owned state is a new state that has been added to it
4. MOESI Protocol : eliminates the requirement for changed data to be written
back to main memory before being shared
Protocols for multi-core system
architectures
5. Firefly Protocol : involves in three states such as Valid-Exclusive,
Shared and Dirty
6. Dragon Protocol : involves in four states : fetch, Exclusive (E) and
Shared clean (Sc) and Modify(M)
7. MECSIF Protocol : custom developed hybrid cache coherence
method that employs both directory and snoopy protocols
Challenges in cache coherency
Detecting certain sharing patterns in order to improve
coherence
Workload heterogeneity is taken into account while
designing coherence protocols
Adapting area-effective directory architecture to assure
scalability of on-chip directory storage
Optimizing data placement strategy in a multi-core
cache system to reduce distant cache visits by bringing
private data closer to the "home core" and reducing data
migration operations in the coherence protocol.
Conclusion
The different coherence maintenance strategies exploited in
multi-cores are investigated
This work aids researchers in comprehending coherence
processes and investigating the implementation issues
provided by the rapidly expanding number of cores.
Despite significant progress in this field, it remains a very
active study topic.
Many research areas exist, such as protocol correctness
verification, performance assessment, comparison, directory
size, and protocol overhead minimization that has to be
looked at in the future.
