Observability & Controllability

• Observability:
• Ease of observing a node by watching external output pins of
the chip
• This metric is relevant when you want to measure the output of
a gate within a larger circuit to check that it operates correctly.
• Given the limited number of nodes that can be directly
observed, it is the aim of good chip designers to have easily
observed gate outputs.
• Adoption of some basic design for test techniques can aid
tremendously in this respect.
• Ideally, you should be able to observe directly or with
moderate indirection (i.e., you may have to wait a few cycles)
every gate output within an integrated circuit.
• While at one time this aim was hindered by the expense of
extra test circuitry and a lack of design methodology.
12: Design for Testability 1
 Controllability
• Controllability: ease of setting a node to 0 or 1 by driving input pins of the
chip.
• This metric is of importance when assessing the degree of difficulty of
testing a particular signal within a circuit.
• An easily controllable node would be directly settable via an input pad.
• A node with little controllability, such as the most significant bit of a counter,
might require many hundreds or thousands of cycles to get it to the right
state.
• Often, you will find it impossible to generate a test sequence to set a
number of poorly controllable nodes into the right state. It should be the aim
of good chip designers to make all nodes easily controllable.
• In common with observability, the adoption of some simple design for test
techniques can aid in this respect tremendously.
• Making all flip-flops resettable via a global reset signal is one step toward
good controllability.
• Combinational logic is usually easy to observe and control.
• Finite state machines can be very difficult, requiring many cycles to enter
desired state Especially if state transition diagram is not known to the test
engineer
12: Design for Testability 2
 Repeatability & Survivability
• The repeatability of system is the ability to produce the same outputs
given the same inputs.
• Combinational logic and synchronous sequential logic is always
repeatable when it is functioning correctly.
• Testing is much easier when the system is repeatable. Some
systems with asynchronous interfaces have a lock-step mode to
facilitate repeatable testing.
• The survivability of a system is the ability to continue function after a
fault.
• For example, error-correcting codes provide survivability in the event
of soft errors. Redundant rows and columns in memories and spare
cores provide survivability in the event of manufacturing defects.
• Adaptive techniques provide survivability in the event of process
variation.
• Some survivability features are invoked automatically by the
hardware, while others are
• activated by blowing fuses after manufacturing test.
12: Design for Testability 3
 Test Pattern Generation
• Manufacturing test ideally would check every node in
the circuit to prove it is not stuck.
• Apply the smallest sequence of test vectors necessary
to prove each node is not stuck.

• Good observability and controllability reduces number

of test vectors required for manufacturing test.
– Reduces the cost of testing
– Motivates design-for-test

12: Design for Testability 4

 Test Example
SA1 SA0 A3 n1
A2
• A3 {0110} {1110} Y

• A2 {1010} {1110} A1
n2 n3

A0
• A1 {0100} {0110}
• A0 {0110} {0111}
• n1{1110} {0110}
• n2{0110} {0100}
• n3{0101} {0110}
• Y {0110} {1110}

• Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

12: Design for Testability 5

 Design for Test
• Design the chip to increase observability and controllability.
• If each register could be observed and controlled, test
problem reduces to testing combinational logic between
registers.
• Better yet, logic blocks could enter test mode where they
generate test patterns and report the results automatically.
• We will first cover three main approaches to what is
commonly called Design for Testability (DFT). These
may be categorized as follows:
• Ad hoc testing
• Scan-based approaches
• Built-in self-test (BIST)

12: Design for Testability 6

 Design for Test
• A technique classified in this category is the use of the
bus in a bus-oriented system for test purposes.
• Each register has been made loadable from the bus and
capable of being driven onto the bus. Here, the internal
logic values that exist on a data bus are enabled onto
the bus for testing purposes.
• Frequently, multiplexers can be used to provide
alternative signal paths during testing.
• In general, ad hoc testing techniques represent a bag of
tricks developed over the years by designers to avoid the
overhead of a systematic approach to testing.

12: Design for Testability 7

 Ad Hoc Testing
• Ad hoc test techniques are collections of ideas aimed at
reducing the combinational explosion of testing.
• They are only useful for small designs where scan,
ATPG( automatic test pattern Generation), and BIST( Built-in-
Selt Test) are not available.
• A complete scan-based testing methodology is
recommended for all digital circuits.
• Following are common techniques for ad hoc testing:
• Partitioning large sequential circuits
• Adding test points
• Adding multiplexers
• Providing for easy state reset
 Scan-Based Techniques
• As discussed earlier, the controllability and observability can be enhanced by providing
more accessible logic nodes with use of additional primary input lines and
multiplexors.

• However, the use of additional I/O pins can be costly not only for chip fabrication but
also for packaging.
• A popular alternative is to use scan registers with both shift and parallel load
capabilities.
• The scan design technique is a structured approach to design sequential circuits for
testability.
• The storage cells in registers are used as observation points,
control points, or both.
• By using the scan design techniques, the testing of a sequential
circuit is reduced to the problem of testing a combinational circuit.
• In the scan-based design, the storage elements are connected to form a long serial
shift register, the so-called scan path.
 Scan-Based Techniques
• In the test mode, the scan-in signal is clocked into the scan path,
and the output of the last stage latch is scanned out. In the normal
mode, the scan-in path is disabled and the circuit functions as a
sequential circuit. The testing sequence is as follows:
•Step 1: Set the mode to test and, let latches accept data
from scan-in input,
Step 2: Verify the scan path by shifting in and out the test
data.
Step 3: Scan in (shift in) the desired state vector into the
shift register.
Step 4: Apply the test pattern to the primary input pins. I : ;
Step 5: Set the mode to normal and observe the primary
outputs of the circuit after sufficient time for propagation.,
Step 6: Assert the circuit clock, for one machine cycle to
capture the outputs of the combinational logic into the
registers.
Step 7: Return to test mode; scan out the contents of the
registers, and at the same time scan in the next pattern.
The general structure of scan-
Step 8: Repeat steps 3-7 until all test patterns are applied.
based design.
 Scan-Based Techniques
• The storage cells in scan design can be implemented using edge-
triggered D flipflops, master-slave flip-flops, or level-sensitive latches
controlled by complementary clock signals to ensure race-free operation.
• Figure given below shows a scan-based design of an edge-triggered D
flip-flop.
• In large high-speed circuits, optimizing a single clock signal for skews,
etc.,both for normal operation and for shift operation, is difficult.
• To overcome this difficulty, two separate clocks, one for normal operation
and one for shift operation, are used.
• Since the shiftoperation does not have to be performed atthe target
speed, its clock is much less constrained.

Scan-based design of an edge-triggered D flip-flop.

 Scan-Based Techniques
• An important approach among scan-based designs is the level sensitive scan design
(LSSD), which incorporates both the level sensitivity and the scan path approach using
shift registers. The level sensitivity is to ensure that the sequential circuit response is
independent of the transient characteristics of the circuit, such as the component and
wire
delays. Thus, LSSD removes hazards and races. Its ATPG is also simplified since tests
have to be generated only for the combinational part of the circuit.
• The boundary scan test method is also used for testing printed circuit boards (PCBs)
and multichip modules (MCMs) carrying multiple chips. Shift registers are placed in each
chip close to I/O pins in order to form a chain around theboard for testing. With successful
implementation of the boundary scan method, a simpler tester can be used for PCB
testing.
On the negative side, scan design uses more complex latches, flip-flops, I/O pins, and
interconnect wires and, thus, requires more chip area. The testing time per test pattern
is also increased due to shift time in long registers.
 Scan-Based Techniques
• An important approach among scan-based designs is the level sensitive scan design
(LSSD), which incorporates both the level sensitivity and the scan path approach
using shift registers.
• The level sensitivity is to ensure that the sequential circuit response is independent
of the transient characteristics of the circuit, such as the component and wire delays.
• Thus, LSSD removes hazards and races.
• Its ATPG is also simplified since tests have to be generated only for the
combinational part of the circuit.
• The boundary scan test method is also used for testing printed circuit boards (PCBs)
and multichip modules (MCMs) carrying multiple chips.
• Shift registers are placed in each chip close to I/O pins in order to form a chain
around theboard for testing. With successful implementation of the boundary scan
method, a simpler tester can be used for PCB testing.

• On the negative side, scan design uses more complex latches, flip-flops, I/O pins,
and interconnect wires and, thus, requires more chip area.
• The testing time per test pattern is also increased due to shift time in long registers.
 Summary-Scan
• Convert each flip-flop to a scan register
CLK
– Only costs one extra multiplexer SCAN

Flop
• Normal mode: flip-flops behave as usual SI
D
Q

• Scan mode: flip-flops behave as shift register

scan-in

• Contents of flops

Flop

Flop
Flop

Flop

Flop
Flop
can be scanned inputs
Logic
Cloud
Logic
Cloud outputs

out and new

Flop

Flop
Flop

values scanned

Flop

Flop
Flop

in scanout

12: Design for Testability 14

 Scannable Flip-flops
SCAN
SCAN CLK Q
 
D
D 0 Flop X
Q Q
SI 1 SI  
(a)  

(b)
 

d

 D
 Q
d
SCAN
d X
Q
s  
s 
SI
(c)
s
 

12: Design for Testability 15

 ATPG
• Test pattern generation is tedious
• Automatic Test Pattern Generation (ATPG) tools
produce a good set of vectors for each block of
combinational logic
• Scan chains are used to control and observe the blocks
• Complete coverage requires a large number of
vectors, raising the cost of test
• Most products settle for covering 90+% of potential
stuck-at faults

12: Design for Testability 16

 Built-in Self-test
• Built-in self-test are used to test the circuit itself.. Online
BIST is used to perform the test under normal operation,
whereas off-line BIST is used to perform the testoff-line.
• The essential circuit modules required for BIST include:
*Pseudo random pattern generator (PRPG)
*Output response analyzer (ORA)
The implementation of both PRPG and ORA can be done with
Linear Feedback Shift Registers (LFSRs).

12: Design for Testability 17

 Built-in Self-test
• To test the circuit, test patterns first have to be generated
either by using a pseudo random pattern generator, a weighted
test generator, an adaptive test generator, or other means.
A pseudo random test generator circuit can use an LFSR, as
shown in Fig.

Apseudo-random sequence generator

using LFSR(LinearFeedbackShift A procedure for BIST.
Register)
12: Design for Testability 18
 PRSG (Pseudo-Random Sequence Generator)
• Linear Feedback Shift Register
– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator

Step Y
CLK Y 0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D 1 110
2 101
3 010
4 100
Flops reset to 111
5 001
6 011
7 111 (repeats)

12: Design for Testability 19

 OutputResponse Analyzer

• The on-chip storage of a fault dictionary containing all

test inputs with the corresponding outputs is prohibitively
expensive in terms of the chip area.
• A simple alternative method is to compare the outputs of
two identical circuits for the same input, with one of them
regarded as reference.
• However, if both circuits have the same faults, their
outputs can still match. Such faults cannot be detected
with this technique,
• although,the probability of two identical circuits having
exactly the same faults would be very low.
• In addition to the above circuits for built-in self test, self-
checking design techniques can be used to detect faults
autonomously during on-line operation.
 OutputResponse Analyzer

• Usually a checker circuit is inserted such that the checker

generates and sends out a signal when on-line faults occur.
• The distribution of checkers throughout a very large digital
circuit or system can provide prompt detection of the fault
location by tracing the checker which sent the fault signal.
• The use of self-checking circuits simplifies the development of
software diagnostic programs.
• However, some additional hardware is required, and the
checker itself needs to have self-checking capability.
• When self-checking capability of the checker itself is required, a
single-output checker is not sufficient since that output may have a
stuck-at fault, thus preventing the detection of actual faults in the
circuit under test.
• A checker with a pair of outputs can be used instead to overcome
this problem.
 Built-In Logic Block Observer
•The built-in logic block observer (BILBO) register is a form of ORA(OutputResponse
Analyzer) which can be used in each cluster of partitioned registers. A basic BILBO circuit is
shown in fig. which allows four different modes controlled by C0 and C1 signals.
The BILBO operation allows monitoring of circuit operation through exclusiveORing
into LFSR at multiple points, which corresponds to the signature analyzer with
multiple inputs.

•Figure 16.14. 3-bit built-in logic observer (BILBO) example.

•Co C1, Mode
0 0 linear shift
1 0 signature analysis
1 1 data (complemented) latch
0 1 reset
 BILBO(Built-In Logic Block Observer)
• Built-in Logic Block Observer
– Combine scan with PRSG & signature analysis
D[0] D[1] D[2]

C[0]
C[1]

Q[2] / SO
Flop

Flop

Flop
SI 1
0 Q[0]
Q[1]

MODE C[1] C[0]

Scan 0 0
Logic Signature
PRSG Test 0 1
Cloud Analyzer
Reset 1 0
Normal 1 1

12: Design for Testability 23

 Boundary Scan
• Testing boards is also difficult
– Need to verify solder joints are good
• Drive a pin to 0, then to 1
• Check that all connected pins get the values
• Through-hold boards used “bed of nails”
• SMT and BGA boards cannot easily contact
pins
• Build capability of observing and controlling
pins into each chip to make board test easier

12: Design for Testability 24

Boundary Scan Example
PackageInterconnect

CHIP B CHIP C

Serial Data Out

CHIP A CHIP D

IO pad and Boundary Scan

Cell

Serial Data In

12: Design for Testability 25

 Boundary Scan Interface
• Boundary scan is accessed through five pins
– TCK: test clock
– TMS: test mode select
– TDI: test data in
– TDO: test data out
– TRST*: test reset (optional)

• Chips with internal scan chains can access the chains

through boundary scan for unified test strategy.

12: Design for Testability 26

 Testing Your Class Project
• Presilicon Verification
– Test vectors: corner cases and random vectors
– HDL simulation of schematics for functionality
– Use 2-phase clocking to avoid races
– Use static CMOS gates to avoid electrical failures
– Use LVS to ensure layout matches schematic
– Don’t worry about timing
• Postsilicon Verification
– Run your test vectors on the fabricated chip
– Use a functional chip tester
– Potentially use breadboard or PCB for full system

12: Design for Testability 27

 TestosterICs
• TestosterICs functional chip tester
– Designed by clinic teams and David Diaz at HMC
– Reads your test vectors, applies them to your chip,
and reports assertion failures

12: Design for Testability 28

 Summary
• Think about testing from the beginning
– Simulate as you go
– Plan for test after fabrication

• “If you don’t test it, it won’t work!

(Guaranteed)”

12: Design for Testability 29