Computer Instructions

and
Control Unit

1
BASIC COMPUTER INSTRUCTIONS CATEGORIES
• Instructions may be placed in several different kinds of categories based on
location of instructions.
— Register reference : - Referencing CPU registers for data processing.
— Memory reference : Referencing memory for data processing.
— I/O reference : program that interact with peripheral devices for data
processing.
Memory-Reference Instructions (OP-code = 000 ~ 110)
15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0 2
1 1 1 1 I/O operation
 Instructions

BASIC COMPUTER INSTRUCTIONS

Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag 3
ION F080 Interrupt on
IOF F040 Interrupt off
CONTROL UNIT
 CPU is partitioned into Arithmetic Logic Unit (ALU) and
Control Unit (CU).
 The function of control unit : -
 Generate relevant timing and control signals to all operations in the
computer.
 It controls the flow of data between the processor and memory and
peripherals.
 Control units are implemented in one of two ways
 Hardwired Control
 CU is made up of sequential and combinational circuits to generate the
control signals
 Microprogrammed Control
 A control memory on the processor contains microprograms that activate the
necessary control signals 4
 Timing and control

TIMING AND CONTROL

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0 Control
I Combinational Signals
D7 Control
logic Read, write, load, inc, clear…..
T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter 5
(SC) Clock
 Timing and control
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
-The SC can be incremented or cleared.
-- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR 6
SC
 TIMING AND CONTROL
 Step1: Where do we fetch the next instruction from
at T0 (start time)?

 The Program Counter register (PC) is assumed to hold the

address of the next instruction to be executed.

 The PC is transferred to the Address Register (AR) which is

connected to the Address Bus Multiplexer.

T0 : AR = PC
 Timing and Control
• Step 2: How do we obtain the instruction from
memory at T1?
– The data stored at the selected address is transferred onto the
Data Bus and then to the Instruction Register (DR) in the
CPU.
T1 : IR = M[AR] ,PC = PC + 1

Memory
Data bus
INC
M[AR] IR LD PC

CPU bus
AR LD
Address bus
 Timing and Control
• Step 3: How do we decode the instruction intention (ie.
meaning, operational definition) at T2?
– The OpCode, Mode and Address field bits all serve as inputs
to the Control Logic Gates that select the specific instruction
semantics NOTE:
• Direct addressing All instructions share the steps
• Indirect addressing T0, T1 and T2.
• CPU register addressing However, depending on what
• Input each specific instruction
requires, the control logic for
• Output higher time steps is more
complicated, requiring more
inputs.
T2 : {D0,...,D7} = DEC( IR(12-14) ),
AR = IR(0-11),
I = IR(15)
INSTRUCTION CYCLE

 In Basic Computer, a machine instruction is executed

in the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction and calculate effective address (EA)
3. Read the EA from memory if the instruction has an indirect address
(Fetch operand)
4. Execute the instruction

 After an instruction is executed, the cycle starts again

at step 1, for the next instruction

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 Instruction Cycle

FETCH AND DECODE

• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)

T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1
S2
T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock 11
Common bus
 Instrction Cycle

DETERMINE THE TYPE OF INSTRUCTION

Start
SC 

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference) =>opcode ≠ 111

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
12
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T 3 when I = 1

- The execution of MR instruction starts with T4

AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand 13
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
 MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0 **
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
D5T4: M[AR]  PC, PC  AR + 1
D5T5: PC  AR, SC 
Memory, PC,0AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

14
1 BUN 135 1 BUN 135
Memory Memory
 Memory Reference Instructions
• Branch UNconditional instruction
– I = 0 :: Replace PC by address in IR(0-11)
– I = 1 :: Replace PC by the address found at the address in IR(0-11)
• That is :: PC = M[ M[ IR(0-11) ] ]

Operation Codes
Direct Indirect
I=0 I=1 Mnemonic RTL
4 C BUN AR = IR(0-11)
PC = AR

PC
IR
I=1 I=0
M
Data DR

Address bus
AR
MUX
 Memory Reference Instructions
• Branch and SAve instruction
– Used for programming subroutine calls
Operation Codes
Direct Indirect
I=0 I=1 Mnemonic RTL
5 D BSA AR = IR(0-11)
M[AR] = PC , PC = AR + 1

(a) BEFORE SUBROUTINE CALL (b) AFTER SUBROUTINE CALL

M M

PC Subr. call instr. PC Subr. call instr.

Return addr.
Subr. entry instr. Subr. entry instr.
 Memory Reference Instructions
• Increment and Skip if Zero instruction
– Used to implement a counter based <do-while> construct
I=0 I=1 Mnemonic RTL
6 E ISZ AR = IR(0-11) , DR = M[AR]
AC = DR , AC = AC + 1 , DR = AC
M[AR] = DR , (AC=0) : PC = PC + 1

(a) BEFORE (b) AFTER

M M

PC Current instr. PC < 0 Current instr.

Branch instr. Branch instr.

Continue instr. Continue instr.

=0
AR AR
Data value Data value + 1
 Instruction Cycle

REGISTER REFERENCE INSTRUCTIONS

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1) 18

SZE rB1: if (E = 0) then (PC  PC+1)

HLT rB0: S  0 (S is a start-stop flip-flop)
FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5
PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0) 19
then (PC  PC + 1)
SC  0