College of engineering and technology

Department of computer science and engineering

Multicore processor
By:
Dilesh kumar sahoo
6th sem
0801106227
 College of engineering and technology
Department of computer science and engineering

Outline
Over view
Design
Performance
Advantages and disadvantages
Examples
Conclusion
Bibliography

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering
Processor : history

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Multicore processor overview

.

A multi-core processor is composed of two or more

independent cores. One can describe it as an integrated
circuit which has two or more individual processors 
Each core has it’s own complete set of resources, and
may share the on-die cache layers

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Windows task manager

Core 2

Core 1

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Why Using Multicore Processor

Drawbacks of Unicore Processors

Difficult to make single-core clock frequencies even

higher.
Many new applications are multithreaded
Deeply pipelined circuits :
Heat problems
Speed of light problems
Difficult design and verification
Large design teams necessary
Server farms need expensive air-conditioning
Dilesh kumar sahoo 14 th april 2011
 College of engineering and technology
Department of computer science and engineering

moore’s law

Moore's law describes a long-term trend in

the history of computing hardware. 
The number of transistors that can be
placed inexpensively on an integrated
circuit has doubled approximately every
two years.
he trend has continued for more than half a
century and is not expected to stop until
Dilesh kumar sahoo
2015 or later. 14 th april 2011
 College of engineering and technology
Department of computer science and engineering

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Single core cpu chip

CPU chip
register file
A The single core
L
U System bus

bus interface

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Multicore architecture
Core 1 Core 2 Core 3 Core 4
Register file Register file Register file Register file
A A A A
L L L L
U U U U

Bus interface

Dilesh kumar sahoo Multi-core CPU chip 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Multicore processor architecture of amd

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Design
S
R CACHE CORE 1
Q

D D M S
CROSS R CACHE CORE 2
R R C Q
BAR
A A T
S
M M R CACHE CORE 3
Q

S
R CACHE CORE 4
Q

Coherent hyper Coherent hyper Coherent hyper

transport transport transport

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

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 College of engineering and technology
Department of computer science and engineering

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 College of engineering and technology
Department of computer science and engineering
 College of engineering and technology
Department of computer science and engineering

.
 College of engineering and technology
Department of computer science and engineering
Within each core, threads are time-sliced (just like on a
uniprocessor
Several threads Several threads Several threads Several threads

c c c c
o o o o
r r r r
e e e e
1 2 3 4

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering
Single core vs multicore
Single core Multicore
processor processor
Vdd 1.0V 1.0V
I/O pins(total) 1280 3000(Estimated)
Opearting 7.8Ghz 4Ghz
Frequency
Chip package data 7.8 GBps 4Gbps
rate
Bandwidth 125Gbps 1 TBps
Power 429.78W 107.39W
Total no of pins on 3840 9000(Estimated)
the chip
Number of pins 2480 4500(Estimated)
On the package
Dilesh kumar sahoo 14 th april 2011
 College of engineering and technology
Department of computer science and engineering

CORE COMPONENTS

Functional units
Superscalar is known territory. Diminishing returns for adding
more functional blocks. Single-threaded architectural performance
is pegged

Data paths
Increasing bandwidth between functional units in a core
makes a difference. Such as comprehensive 64-bit design.

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Pipeline
Deeper pipeline buys frequency at expense of increased cache miss
penalty and lower instructions per clock. Shallow pipeline gives better
instructions per clock at the expense of frequency scaling. Max.
frequency per core requires deeper pipelines

Cache
Cache size buys performance at expense of die size. Deep pipeline
cache miss penalties are reduced by larger caches.

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering
ADVANTAGES
 Proximity of multiple CPU cores on the same die have the advantage that the cache
circuitry can operate at a much higher clock rate than is possible if the signals have to
travel off-chip

 Assuming that the die can fit into the package, physically, the multi-core CPU designs
require much less PCB space than multi-chip SMP design.

 A dual-core processor uses slightly less power than two coupled single-core
processors, principally because of the increased power required to drive signals
external to the chip and because the smaller silicon process geometry allows the cores
to operate at lower voltages.
 In terms of competing technologies for the available silicon die area, multi-core
design can make use of proven CPU core library designs and produce a product with
lower risk of design error than devising a new wider core design
Dilesh kumar sahoo 14 th april 2011
 College of engineering and technology
Department of computer science and engineering
ADVANTAGES
 In terms of competing technologies for the available silicon die area, multi-core
design can make use of proven CPU core library designs and produce a product with
lower risk of design error than devising a new wider core design

 Increased computing capabilities.

 New benefits for both home and business.

 Unlimited opportunities to explore avenues in the digital enterprise.

 Increased productivity of offices

 Digitalization of homes.

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering
DISADVANTAGES
 In addition to operating system (OS) to support, adjustments to existing
software are required to maximize utilization of the computing resources
provided by multi-core processors. Also, the ability of multi-core
processors to increase application performance depends on the use of
multiple threads within applications.
 They are more difficult to manage thermally than lower-density single-
chip designs.
 From an architectural point of view, ultimately, single CPU designs may
make better use of the silicon surface area than multiprocessing cores, so
a development commitment to this architecture may carry the risk of
obsolescence
 They donot work n times as that of single processors.
N= no of processor cores

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

application

 Database servers
 Web servers (Web commerce)
 Compilers
 Video editing
 Encoding .
 3D gaming.
 Powerful graphics solution
 The full effect and the advantage of having a multi-core processor,
when it is used together with a multithreading operating .
 Multimedia applications
 Scientific applications, CAD/CAM
 In general, applications with Thread-level parallelism
(as opposed to instruction-level parallelism)

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

Each can run

on own cores
Dilesh kumar sahoo 14 th april 2011
 College of engineering and technology
Department of computer science and engineering
Challenges

Having multiple cores on a single chip gives some challenges .

 Power and temperature management

 Memory/cache coherence is another challenge
 And finally, using a multicore processor to its full potential is
another issue

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

conclusion

 Multi-core chips an important new

trend in computer architecture

 Several new multi-core

chips in design phases

 Parallel programming techniques

likely to gain importance

Dilesh kumar sahoo 14 th april 2011

 College of engineering and technology
Department of computer science and engineering

reference
[1]L Hammond, BA Nayfeh, K Olukotun, “A Single-Chip Multiprocessor,”
IEEE, Sept 1997.

[2] P. Frost Gorder, “Multicore Processors for Science and Engineering”,

IEEE CS, March/April 2007

[3] D. Geer, “Chip Makers Turn to Multicore Processors”, Computer, IEEE

Computer Society, May 2005

[4] R. Merritt, “CPU Designers Debate Multi-core Future”, EETimes Online,

February 2008, [Link]
articleID=206105179

[5] R. Merritt, “X86 Cuts to the Cores”, EETimes Online, September 2007,
[Link]

Dilesh kumar sahoo 21th April 2011