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Biasing Circuits of FET

The document discusses voltage-divider bias circuits for field-effect transistors (FETs). It describes how the voltage-divider bias circuit works by using two resistors, Rg1 and Rg2, to form a potential divider across the drain supply voltage. This divides the voltage and provides the necessary bias voltage at the gate of the FET. The document also provides equations for calculating the quiescent drain current, gate-source voltage, and drain-source voltage of a JFET amplifier using this biasing method.

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Monica Gunjal
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526 views10 pages

Biasing Circuits of FET

The document discusses voltage-divider bias circuits for field-effect transistors (FETs). It describes how the voltage-divider bias circuit works by using two resistors, Rg1 and Rg2, to form a potential divider across the drain supply voltage. This divides the voltage and provides the necessary bias voltage at the gate of the FET. The document also provides equations for calculating the quiescent drain current, gate-source voltage, and drain-source voltage of a JFET amplifier using this biasing method.

Uploaded by

Monica Gunjal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Biasing circuits of FET

1.     Fixed bias circuits


2.     Self bias circuits
3.     Voltage bias circuits
Voltage -Divider Bias circuits
Voltage -Divider Bias circuits
• The resistors RGl and RG2 form a potential divider across drain supply
VDD.
• The voltage V2 across RG2 provides the necessary bias.
• The additional gate resistor RGl from gate to supply voltage facilitates in
larger adjustment of the dc bias point and permits use of larger valued
RS.
• The coupling capacitors are assumed to be open circuit for DC analysis
Voltage -Divider Bias circuits
• The gate is reverse biased so that IG = 0 and gate voltage
VG = (VDD/R G1 + R G2 ) *RG2
• Applying KVL to the input circuit we get
VGS= VG – VS = VG - ID RS

IDQ= IDSS(1- VGS/ VP)2


 
VDS = VDD – ID (RD + RS)
• The operating point of a JFET amplifier using the Voltage -Divider Bias is determined by
IDQ= IDSS(1- VGS/ VP)2
VDSQ = VDD – ID (RD + RS)
VGSQ = VG – ID RS
Voltage -Divider Bias circuits
• Determine IDQ, VGSQ, VD, VS, VDS, and VDG
Example 2:
Example no.3
Calculate

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