+
Chapter 7
Input/Output
+
Generic
Model
of an I/O Module
+
External Devices
Provide a means of exchanging
Three categories:
data between the external Human readable
environment and the computer Suitable for communicating with the
computer user
Attach to the computer by a link to Video display terminals (VDTs), printers
an I/O module
The link is used to exchange control, Machine readable
status, and data between the I/O Suitable for communicating with
module and the external device equipment
Magnetic disk and tape systems, sensors
peripheral device and actuators
An external device connected to an Communication
I/O module
Suitable for communicating with remote
devices such as a terminal, a machine
readable device, or another computer
+
External
Device
Block
Diagram
+ Most common means of
computer/user interaction
Keyboard/Monitor User provides input through the
keyboard
The monitor displays data provided by
International Reference Alphabet the computer
(IRA)
Basic unit of exchange is the character Keyboard Codes
Associated with each character is a code
When the user depresses a key it generates an
Each character in this code is represented by electronic signal that is interpreted by the
a unique 7-bit binary code transducer in the keyboard and translated into
128 different characters can be represented the bit pattern of the corresponding IRA code
This bit pattern is transmitted to the I/O module
Characters are of two types:
in the computer
Printable
Alphabetic, numeric, and special On output, IRA code characters are transmitted
characters that can be printed on paper or to an external device from the I/O module
displayed on a screen The transducer interprets the code and sends the
Control required electronic signals to the output device
Have to do with controlling the printing or either to display the indicated character or
displaying of characters perform the requested control function
Example is carriage return
Other control characters are concerned
with communications procedures
I/O Modules Control and
timing
• Coordinates the flow
Module Function of traffic between
internal resources and
external devices
Processor
Error detection communication
• Detects and reports • Involves command
transmission errors decoding, data, status
The major reporting, address
recognition
functions for an
I/O module fall
into the
following
categories:
Data buffering Device
• Performs the needed communication
buffering operation to • Involves commands,
balance device and status information,
memory speeds and data
I/O Module Structure
+
Programmed I/O
Three techniques are possible for I/O operations:
Programmed I/O
Data are exchanged between the processor and the I/O module
Processor executes a program that gives it direct control of the I/O operation
When the processor issues a command it must wait until the I/O operation is
complete
If the processor is faster than the I/O module this is wasteful of processor
time
Interrupt-driven I/O
Processor issues an I/O command, continues to execute other instructions,
and is interrupted by the I/O module when the latter has completed its work
Direct memory access (DMA)
The I/O module and main memory exchange data directly without processor
involvement
Table 7.1
I/O Techniques
+
+
I/O Commands
There are four types of I/O commands that an I/O module may receive when
it is addressed by a processor:
1) Control
- used to activate a peripheral and tell it what to do
2) Test
- used to test various status conditions associated with an I/O module and its
peripherals
3) Read
- causes the I/O module to obtain an item of data from the peripheral and place
it in an internal buffer
4) Write
- causes the I/O module to take an item of data from the data bus and
subsequently transmit that data item to the peripheral
Three
Techniques
for Input of a
Block of Data
I/O Instructions
With programmed I/O there is a close correspondence between the I/O-related instructions
that the processor fetches from memory and the I/O commands that the processor issues to an
I/O module to execute the instructions
Each I/O device connected through I/O modules is given a unique
identifier or address
The form of the When the processor
issues an I/O command,
Memory-mapped I/O
instruction depends on
the way in which the command contains
external devices are the address of the desired
addressed device
Thus each I/O module There is a single address space for memory A single read line and a single write line are
must interpret the address locations and I/O devices needed on the bus
lines to determine if the
command is for itself
+
I/O Mapping Summary
Memory mapped I/O
Devices and memory share an address space
I/O looks just like memory read/write
No special commands for I/O
Large selection of memory access commands available
Isolated I/O
Separate address spaces
Need I/O or memory select lines
Special commands for I/O
Limited set
Memory
Mapped
I/O
Isolated
I/O
+
Interrupt-Driven I/O
The problem with programmed I/O is that the processor has to wait a long
time for the I/O module to be ready for either reception or transmission of
data
An alternative is for the processor to issue an I/O command to a module
and then go on to do some other useful work
The I/O module will then interrupt the processor to request service when it
is ready to exchange data with the processor
The processor executes the data transfer and resumes its former processing
+
Simple Interrupt
Processing
+
BATAS KELOMPOK
+
Changes
in Memory
and Registers
for an
Interrupt
Design Issues
• Because there will be
multiple I/O modules
how does the
processor determine
Two design which device issued
issues arise in the interrupt?
implementing • If multiple interrupts
interrupt I/O: have occurred how
does the processor
decide which one to
process?
+
Device Identification
Four general categories of techniques are in common use:
Multiple interrupt lines
Between the processor and the I/O modules
Most straightforward approach to the problem
Consequently even if multiple lines are used, it is likely that each line will have multiple I/O modules
attached to it
Softwarepoll
When processor detects an interrupt it branches to an interrupt-service routine whose job is to poll each
I/O module to determine which module caused the interrupt
Time consuming
Daisy chain (hardware poll, vectored)
The interrupt acknowledge line is daisy chained through the modules
Vector – address of the I/O module or some other unique identifier
Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service routine,
avoiding the need to execute a general interrupt-service routine first
Busarbitration (vectored)
An I/O module must first gain control of the bus before it can raise the interrupt request line
When the processor detects the interrupt it responds on the interrupt acknowledge line
Then the requesting module places its vector on the data lines
+
Intel
82C59A
Interrupt
Controller
+ Intel 82C55A
Programmable Peripheral Interface
+
Keyboard/Display
Interfaces to
82C55A
Drawbacks of Programmed and Interrupt-
Driven I/O
Both forms of I/O suffer from two inherent drawbacks:
1) The I/O transfer rate is limited by the speed with
which the processor can test and service a device
2) The processor is tied up in managing an I/O
transfer; a number of instructions must be executed
for each I/O transfer
+
When large volumes of data are to be moved a more efficient
technique is direct memory access (DMA)
+
Typical DMA
Module Diagram
DMA
DMA
+
DMA Operation
+
Alternative
DMA
Configurations
8237 DMA Usage of System Bus
8237 contains four DMA Data does not pass
channels through and is not stored
• Programmed in DMA chip
independently Can do memory to • DMA only between I/O
• Any one active memory via register port and memory
• Numbered 0, 1, 2, and 3 • Not between two I/O
ports or two memory
locations
Fly-By DMA Controller
+
Table 7.2
Intel
8237A Registers
E/D = enable/disable
TC = terminal count
+
BATAS KELOMPOK
+
Evolution of the I/O Function
1. The CPU directly controls a
4. The I/O module is given direct access to
peripheral device.
memory via DMA. It can now move a
2. A controller or I/O module is block of data to or from memory without
involving the CPU, except at the
added. The CPU uses
beginning and end of the transfer.
programmed I/O without
interrupts.
5. The I/O module is enhanced to become a
processor in its own right, with a
3. Same configuration as in step 2
specialized instruction set tailored for I/O
is used, but now interrupts are
employed. The CPU need not 6. The I/O module has a local memory of
spend time waiting for an I/O
its own and is, in fact, a computer in its
operation to be performed, thus
own right. With this architecture a large
increasing efficiency.
set of I/O devices can be controlled with
minimal CPU involvement.
+
I/O
Channel
Architecture
+
Parallel
and
Serial
I/O
Point-to-Point and Multipoint
Configurations
Multipoint external interfaces are
Connection between an I/O Point-to-point interface provides a used to support external mass
module in a computer system and dedicated line between the I/O storage devices (disk and tape
external devices can be either: module and the external device drives) and multimedia devices
(CD-ROMs, video, audio)
On small systems (PCs,
workstations) typical point-
point-to-point to-point links include those Are in effect external buses
to the keyboard, printer,
and external modem
Example is EIA-232
multiport
specification
+
Thunderbolt
Provides up to 10 Gbps throughput
Most recent and fastest peripheral in each direction and up to 10 Watts
connection technology to become of power to connected peripherals
available for general-purpose use
A Thunderbolt-compatible peripheral
Developed by Intel with interface is considerably more
collaboration from Apple complex than a simple USB device
The technology combines data, First generation products are primarily
video, audio, and power into a aimed at the professional-consumer
single high-speed connection for market such as audiovisual editors who
peripherals such as hard drives, want to be able to move large volumes
RAID arrays, video-capture boxes, of data quickly between storage devices
and network interfaces and laptops
Thunderbolt is a standard feature of
Apple’s MacBook Pro laptop and iMac
desktop computers
+
Computer Configuration with Thunderbolt
+
Thunderbolt
Protocol
Layers
+
InfiniBand
Recent I/O specification aimed at the high-end server market
First version was released in early 2001
Standard describes an architecture and specifications for data flow among
processors and intelligent I/O devices
Has become a popular interface for storage area networking and other large
storage configurations
Enables servers, remote storage, and other network devices to be attached
in a central fabric of switches and links
The switch-based architecture can connect up to 64,000 servers, storage
systems, and networking devices
InfiniBand Switch Fabric
+
InfiniBand Operation
Each physical link between a The InfiniBand switch maps traffic
switch and an attached interface from an incoming lane to an
can support up to 16 logical outgoing lane to route the data
channels, called virtual lanes between the desired end points
One lane is reserved for fabric
management and the other lanes
for data transport A layered protocol architecture is
used, consisting of four layers:
A virtual lane is temporarily Physical
dedicated to the transfer of data
from one end node to another over Link
the InfiniBand fabric Network
Transport
+
Table 7.3
InfiniBand Links and Data Throughput
Rates
InfiniBand Communication Protocol Stack
+
zEnterprise 196
Introduced in 2010
IBM’s latest mainframe computer offering
System is based on the use of the z196 chip
5.2 GHz multi-core chip with four cores
Can have a maximum of 24 processor chips (96 cores)
Has a dedicated I/O subsystem that manages all I/O operations
Of the 96 core processors, up to 4 of these can be dedicated for I/O use, creating 4
channel subsystems (CSS)
Each CSS is made up of the following elements:
System assist processor (SAP)
Hardware system area (HSA)
Logical partitions
Subchannels
Channel path
Channel
I/O System Organization
IBM z196 I/O System Structure
+ Summary
Input/Output
Direct memory access
External devices
Drawbacks of programmed and
interrupt-driven I/O
Keyboard/monitor DMA function
Disk drive Intel 8237A DMA controller
I/O modules
Module function I/O channels and processors
I/O module structure The evolution of the I/O function
Programmed I/O Characteristics of I/O channels
Overview of programmed I/O
I/O commands The external interface
I/O instructions Types of interfaces
Interrupt-driven I/O Point-to-point and multipoint
Interrupt processing
configurations
Thunderbolt
Design issues
InfiniBand
Intel 82C59A interrupt controller
Intel 82C55A programmable peripheral
interface
IBM zEnterprise 196 I/O structure
