SIEMENS
BINARY & LOGIC OPERATION
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SIMATIC S7 1/8 July 5, 2021
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Objectives
- Review On The Logic Gates & How It Is represented In LAD, STL, FBD
- Know The Set-Reset Functions.
- Know The Pulse Edge & Mid-Line Coil.
- Know The Jump Condition.
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OR Gate AND Gate
S3 S1 (I 0.0)
(I 0.2)
Circuit
S4 S2 (I 0.1)
(I 0.3) Diagram
L1 L2
L3 (Q 8.2)
(Q 8.0) (Q 8.1)
I 0.2 Q 8.2 I 0.0 I 0.1 Q 8.0
LAD Diagram
I 0.3 Q 8.1
I 0.0 & Q 8.0
I 0.2 >=1 Q 8.2 =
FBD Diagram I 0.1
=
I 0.3 Q 8.1
=
A I 0.0
O I 0.2 A I 0.1
O I 0.3 STL = Q 8.0
= Q 8.2 = Q 8.1
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XNOR Gate XOR Gate
S1 (I 0.6) S1 (I 0.6) Circuit
S1 (I 0.4) S2 (I 0.5)
Diagram
S2 (I 0.7) S2 (I 0.7) S1 (I 0.4)
S2 (I 0.5)
L1 (Q 8.0) L1 (Q 8.0)
I 0.6 I 0.7 Q 8.0 I 0.4 I 0.5 Q 8.0
LAD Diagram
I 0.6 I 0.7
I 0.4 I 0.5
I 0.6 &
I 0.7 >=1 Q 8.0 FBD Diagram &
I 0.4
= Q 8.0
I 0.5 >=1
I 0.6 & =
I 0.7 I 0.4 &
AN I 1.0 I 0.5
AN I 1.1 STL
O X I 0.4
A I 0.6
A I 0.7
X I 0.5
= Q8.0 = Q8.0
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Example:
I0.0 I0.3 I0.5
1- Convert the Following Circuit Diagram to LAD. I0.1
I1.0
2- Convert the LAD Diagram to STL.
I0.2 I0.4
Answer:
1-
I0.6
I0.7
Q0.0
2-
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Exercise:
I1.2 I1.4
1- Convert the Following Circuit Diagram to STL. I0.0
I0.2
I0.5
I0.7
I1.5
I1.3
I0.1 I0.6
I1.0
I0.3
I0.4
I1.1
I1.7 I1.6
Q0.0
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Set Reset
The specified address is set to signal The specified address is reset to
state "1" and remains set until signal state "0" and remains in
another instruction resets the this state until another
address. instruction sets the address
again.
I 0.2 Q 0.0
I 0.0 I 0.1
Q 0.0
LAD Diagram (R)
(S)
I 0.3
I 0.2
I 0.0 & >=1 Q 0.1
Q 0.1 FBD Diagram
S I 0.3 R
I 0.1
A I 0.0 O I 0.2
A I 0.1 O I 0.3
STL R Q 0.2
S Q 0.2
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Setting/Reseting FlipFlop Setting/Reseting FlipFlop
Dominant Set Dominant Reset
M1.0 M1.1
I 0.4 Q 0.2 I 0.4
RS Q 0.3
R Q SR
S Q
I 0.5
LAD Diagram
I 0.5
S R
M1.0
M1.1
RS
I 0.4 R SR
I 0.4 S
Q0.2 FBD Diagram Q0.3
I 0.5 Q = =
S I 0.5 R Q
A I 0.4
A I 0.4
R M 1.0
S M 1.1
A I 0.5 STL A I 0.5
S M 1.0
R M 1.1
A M 1.0
A M 1.1
= Q 0.2
= Q 0.3
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Midline Output Coil
It is an intermediate assignment
element with assignment function
I 0.0 I 0.1 M0.6 I 0.3 I 0.4 M 1.0 Q 0.3
LAD Diagram ( ) NOT ( ) ( )
I 0.0 &
M0.6
I 0.1 &
FBD Diagram I 0.3 M1.0 Q 0.3
I 0.4 =
A I 0.0
A I 0.1
= M 0.6
STL A M 0.6
A I 0.3
A I 0.4
NOT
= M 1.0
A M 1.0
= Q 0.3
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SET CLR NOT
The SET The CLEAR The NOT instruction
instruction sets instruction sets the inverts the RLO.
the RLO to "1" RLO to "0" without
without pre- pre-conditions
conditions
Q0.0
NOt I 0.0 I 0.1
LAD NOt LAD NOT ( )
EXIST EXIST
I 0.0 &
Q0.0
NOt NOt FBD I 0.1 =
EXIST FBD EXIST
A I 0.0
CLR A I 0.1
SET
STL = M 0.5 STL NOT
= M 0.4
= Q0.0
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Negative Edge Detection Positive Edge Detection
I 1.0 I 1.1 M1.0 M0.2 I 0.0 I 0.1 M0.0 M0.1
N LAD P
Diagram
I 1.0 & I 1.0 &
M1.1 M0.2 M1.0 M0.1
I 1.1 N = FBD I 1.1 P =
Diagram
A I 1.0
A I 1.1 A I 1.0
FN M1.1
STL A I 1.1
FP M1.0
= M0.2 = M0.1
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Positive Edge Examples 1:
(Positive Edge Detection) detects a
signal change in the address (M0.1)
OB1-Cycle
from "0" to "1", and displays it as
I 0.0
RLO = "1" after the instruction.
I 0.1
RLO
Negative Edge M1.0
(Negative Edge Detection) detects a M1.1
signal change in the address (M1.1)
from "1" to "0" and displays it as M8.0
RLO = "1" after the instruction M8.1
(such as at M 0.1) for one cycle.
Examples 2:
I 0.0
I 0.1
M1.0
M1.1
OB1-Cycle
M8.0
M8.1
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Network 1
Unconditional Jump M001
( JMP )
In LAD/FBD, the label (M001) is
entered as an identifier
above the coil symbol or Network 2
assignment symbol. LAD :
In STL it comes after the Jump Diagram :
(JU) instruction. Network n
An unconditional jump
instruction causes a program
jump to a label regardless of the M001
RLO. M99.7
M50.0 I 44.1
( )
Jump Label
The label may be as many
as four characters of which Network 1
the first character must be JU M001
a letter.
STL
Example: M001: A I 0.0 Network 2
:
:
:
:
Network n
M001: AN M50.0
AN I 44.1
= M99.7
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Network 1
Conditional Jump I 0.0 I 0.1 M002
The "JC" conditional jump is
(JMP)
only executed if the RLO is Network 2
"1". LAD :
Diagram :
The "JCN" conditional jump Network n
is only executed if the RLO is
"0".
M002
Note: M99.7
STL provides additional jump M50.0 I 44.1
operations ( )
Network 1
A I 0.0
A I 0.1
JC M002
STL
Network 2
:
:
:
:
Network n
M002: AN M50.0
AN I 44.1
= M99.7
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Answer of Exercise 1:
Answer of Exercise 3:
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Answer of Exercise 2:
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